Quick VHDL simulation

You can test your VHDL design at this point by using QuickHDL.

1. Type qhsim at the command line.
2. In the Startup window, the settings are:

   Simulator resolution: ns
   Library: work
   Entity, Configuration, or Module: design_name
   Architecture: behavior
   Load
   

3. In the QuickHDL VHDL/Verilog window, in the pull down menu if you go to View you probably want to open:

   Source: To view your source code.
   Signals: To force your inputs.
   Waves: To see the waveforms.
   

4. In the Signals window, use View to list inputs, outputs or internal signals. Go to Wave and Signals in design to trace these in the Wave window.
5. To force a signal, select it, click on Force and then set the value and delays.
6. For a clock you need to force the signal twice. For example, if you want a clock with a period of 40ns that started low you would:
   1. Select the 'clk' signal in the Signals window.
   2. In the menu bar click on Force.
   3. Put 0 in the Value field.
   4. Put 0 in the Delay field.
   5. Enter 40 in the Repeat Every field.
   6. Click on Force
   7. In the menu bar click on Force again.
   8. Put 1 in the Value field.
   9. Put 20 in the Delay field.
   10. Enter 40 in the Repeat Every field.
7. In the main window under Run click on 100 ns to run the simulation.
8. If your design has buses, click on the + in the Wave window to see the individual signals.

After you have verified the functionality of your design go on to the next section.