A VHDL example

LIBRARY mgc_portable;
USE mgc_portable.qsim_logic.ALL;
ENTITY example IS
   PORT (a, b : IN  qsim_state;
	 y    : OUT qsim_state
   );
END example;

ARCHITECTURE simple OF example IS
SIGNAL int1, int2, int3 : qsim_state; -- internal signals -- can be traced.
BEGIN
   nan1: PROCESS(a,b) -- if a or b change value do this
   BEGIN
      int1 <= a NAND b;
   END PROCESS nan1;

   nan23: PROCESS(a,b) -- if a or b change value do this
		       -- ERROR should also execute if int1 changes valuse
   BEGIN
      int2 <= a NAND int1;
      int3 <= int1 NAND b;
   END PROCESS nan23;

   nan4: PROCESS(int2, int3) -- if int2 or int3 change state do this
   BEGIN
      y <= int2 NAND int3;
   END PROCESS nan4;
   END simple;