VLSI System Design (EE575)
Lab 4
 
Static Logic vs. Dynamic Logic vs. Pass Transistor Logic

 

 

1. Objectives

The objective of this lab and the next lab is to design a logic circuit using three different circuit design styles: the static logic style, the dynamic logic style, and the pass transistor logic style. Their performance and operating constraints need to be determined and optimized. This lab deals with static, dynamic, and PTL versions of the implementation.

2. Lab Description and Specs

Function:

A bit-slice full adder with a configuration that can be easily cascaded to form a multi-bit adder. Use full static CMOS logic, PE dynamic logic and pass-transistor logic to implement the function Cn+1 = f(An, Bn, Cn) and Sn = f(An, Bn, Cn, Cn+1). For the dynamic logic implementation, use an n-tree section to generate carry bit and followed by a p-tree section to generate the sum bit. (Hint: take the carry bit generated by the previous n-tree section into the following p-tree section for the sum bit.) Inputs: An, Bn: Adder data input signals,

Cn: Adder carry input,

Clk, Clkbar: clock signal and its complement.

Outputs: (use 100fF output capacitance on each) Sn: Adder sum output,

Cn+1: Adder carry output.

 Deliverables: Schematics from DA for each circuit style.
Output waveforms from schematic simulations showing for each circuit style:
proper circuit functionality at low frequency,
set and hold time measurements (for limiting signal only, where applicable),
proper circuit functionality at max. frequency. Power vs. Delay optimization curve for all circuit styles with 4 points for each curve (indicate your optimal trade off points).
Layouts from IC for each circuit style.
Output waveforms from layout simulations showing for each circuit style:
proper circuit functionality at low frequency,
set and hold time measurements (for limiting signal only),
proper circuit functionality at max. frequency. Compare the operating parameters (setup time, hold time, max. freq., power, etc.) for each circuit style.
Explain the advantages/disadvantages of each circuit style.3. Recommended Procedures For this lab you can use the static CMOS gates from previous labs to implement the adder bit-slice. For the dynamic logic, use one n-section and one p-section. For the pass-transistor logic, use the separated n and p sections. The following lists the recommended steps:
  1. Generate a schematic in DA.
  2. Verify the functionality of the schematic with Esim.
  3. Investigate power vs. delay characteristics:
    Vary overall gate width while maintaining n/p-tree ratio (using ".param" might be VERY useful)
    Choose "optimal" trade-off point (not fastest nor highest power, use your judgement)
  4. Rinse. Repeat for each circuit style.