Digital
System Design (ECE450)
Lab 8
Subway
Signal Control Logic II
(Verilog & Cadence)
1. Objectives
The objective of this lab is to expand the subway signal
control logic by adding a sequential logic to it.
2. Lab Description and Specs
Function:
This is the continuation of Lab 3. In Lab 3, the direction
signal D is given as a primary input signal. Now, let’s design a finite state
machine to generate signal D. Let’s assume that the traffic pattern for the
track is such when two consecutive left-to-right trains passed by, the next
train must go from right-to-left. After that, there will be two more
left-to-right trains, etc. To detect the train direction through the station,
we set up two light beams just above the rail track and place two photocells,
P1 and P2, some distance apart. Assume the train can fit inside of the two
beams. When the beam shines on a photocell, it produces a 0, and when the beam
is blocked, it produces a 1. The train may stop at the middle of the
photocells. If this happens, no change is made to signal D. If the train
stopping at the middle and then back to the direction it came from, then this
train does not count as a passing train. Design a logic circuit to generate D.
Inputs:
P1, P2:
Two photocell outputs.
Reset: Global reset.
Outputs:
D:
The direction control signal as specified in Lab 3.
3. Recommended Procedures
For this lab you will use the Cadence to design and verify your circuit.
4. Prelab
- State Transition Diagram
- Boolean Equations
5. Questions