Digital System Design (ECE450)

Lab 6

Grey Code Counter (Cadence)

1.    Objective

The objective of this lab is to learn simple sequential logic circuit design and verification using schematic capture and digital simulation tools.

2.    Lab Description and Specs

• Function:

Design a 3-bit grey code counter. The counting sequence for grey code is 000, 001, 011, 010, 110, 111, 101, 100. Use D-FFs to implement the counter. 

• Inputs: clock: Clock signal.

• Outputs    o[2:0]: Grey code outputs.

3. Recommended Procedure

1. Draw the state transition diagram for the grey code counter.
2. Map unused states to the initial count of 000.
3. Translate the state transition diagram into a state transition table.
4. Generate a truth table for each D-FF input.
5. Obtain the Boolean equations from the truth table.
6. Draw the corresponding schematic diagram in Cadence.
7. Run Cadence to simulate and verify the functionality of the counter.

4.    Prelab

1. State Transition Diagram
2. State Transition Table
3. Truth Tables
4. Boolean Equations
5. Paper Schematic Drawing

5. Questions

• What is Moore Finite State Machine (FSM).
• What is Mealy FSM.