Digital System Design (ECE450)

Lab 4

 

Logarithmic Multiplier (Verilog)

 

 

1. Objectives

The objective of this lab is to design a complex arithmetic logic block using Verilog.

2. Lab Description and Specs

Function:

Logarithmic multiplier performs multiplication of a pair of input numbers A and B by adding their logarithms as follows:


 
It converts a multiplication function to an addition function. The log and antilog operations can be performed by table lookup in Read Only Memory (ROM). A and B are 5-bit integer numbers. Choose a design that doesn’t require a ROM size that is infeasible by manual design (say, no more than 64 entries). Based on the range of A and B, you should also choose the location of the decimal point for the ROM output. You may have a significant amount of round off error in your ROM table. You can also assume unsigned binary representation of the number.

Inputs:

A, B: 5-bit inputs to the multiplier.

Outputs:

M: Output from the multiplier

F: Overflow flag

3.    Recommended Procedures

For this lab you should design the ROM and the random logic part separately.

    1. Use the Verilog case statement to develop your ROM tables.
    2. Design a carry-look-ahead adder for adding numbers from a data structure to use as outputs of the ROMs.
    3. Design a ROM and use it for both log and antilog table lookup.
    4. Run Cadence to verify the functionality of the multiplier by applying combinations of inputs like those in the truth table.
    5. Implement the entire block including adder and ROM blocks in Verilog.
    6. Download the entire design into Altera protoboard and verify its function.

4.     Prelab

a. Verilog code for the logarithmic multiplier 

 

5. Questions