Digital
System Design (ECE 450)
Lab 1
Three Bit
ALU (Cadence)
1. Objectives
The objective of this lab is to design a bit slice 3-bit Arithmetic Logic Unit (ALU) using Cadence as well as using hierarchical design principles.
2. Lab Description and Specs
Function:
Three-bit addition,
subtraction, XOR (bitwise between A and B), and 3-bit shift-left (on A; shift
in zero at the least significant bit).
Inputs:
fun_sel0 and fun_sel1: Selects
one of the four functions.
ain[2:0]
and bin[2:0]: Inputs for the two 3-bit numbers or one 3-bit number.
Outputs:
out[2:0]: The three-bit number that
is the result of the ALU operation.
3. Recommended Procedures
For
this lab you will use logic synthesis to design a 1-bit ALU block that performs
the four functions on two one-bit inputs. You will then cascade three of these
blocks together to form the 3-bit ALU along with the control decoding logic and
the output decoding block.
4.
Prelab
5. Questions