Digital System Design (ECE 450)

Lab 1

 

Three Bit ALU (Cadence)

 

 

1. Objectives

The objective of this lab is to design a bit slice 3-bit Arithmetic Logic Unit (ALU) using Cadence as well as using hierarchical design principles.

2. Lab Description and Specs

Function:

Three-bit addition, subtraction, XOR (bitwise between A and B), and 3-bit shift-left (on A; shift in zero at the least significant bit).

Inputs:

fun_sel0 and fun_sel1: Selects one of the four functions.
ain[2:0] and bin[2:0]: Inputs for the two 3-bit numbers or one 3-bit number.
 

Outputs:

out[2:0]: The three-bit number that is the result of the ALU operation.
 

3. Recommended Procedures

For this lab you will use logic synthesis to design a 1-bit ALU block that performs the four functions on two one-bit inputs. You will then cascade three of these blocks together to form the 3-bit ALU along with the control decoding logic and the output decoding block.

    1. Write out the truth table to perform the 1-bit ALU and perform the logic minimization process to obtain the minimum Boolean equations.
    2. Map the Boolean equations to a schematic sheet using CADENCE.
    3. Run Cadence to verify the functionality of the 1-bit ALU block by applying every combination of inputs like those in the truth table.
    4. Check the sheet prior to making a symbol. Make a symbol for the 1-bit ALU using CADENCE.
    5. Open a new schematic sheet. Cascade three 1-bit ALUs to form a 3-bit ALU.
    6. Check the sheet prior to making a symbol. Make a new symbol for the 3-bit ALU. Note that the data ports should now be 3-bit wide bus.


4. Prelab

  1. Truth table and equations for 1-bit ALU.
  2. Paper Logic Schematic of 1-bit ALU.
  3. Paper Schematic of 3-bit ALU, using 1-bit slices.

5. Questions