The Challenge

The fully digital Silver Cloud was a smashing success, and Banana Electronics  has decided to embark on a nanoprocessor design. Examples of programmable processors include microprocessors in your computer. Your task is to design a nanoprocessor that can execute simple programs. You have already designed many of the modules required in previous projects, e.g.,  adder/subtractor, multiplier, register bank and ROM based SSD decoder, which will be reused in this design.  After completion of the design, establish the functionality of your design through  simulation and hardware implementation.
This is your last official Banana project, so this is your last opportunity to prepare an excellent report as explained in another link of this website.

BACKGROUND:

A microprocessor is the core functional unit (often called the brain) of any computer.  They are also widely used in many processing devices, appliances, automobiles, etc.  A microprocessor is a programmable device that executes sets of instructions (software).    A program consists of a sequence of instructions that the microprocessor carries out. Each instruction corresponds to a simple operation such as addition, multiplication or data movement.
Example A: The  instruction IN R1,5  causes microprocessor to load the value '5' into  register R1
Example B: The instruction OUT R2  to displays the value in register R2 on the seven-segment display.

Using a series of such  instructions  more complex computations can be carried out.
You will be designing a very simple processor (ECE102 nanoprocessor) capable of carrying out a small set of instructions.
Examples A and B above will be used to explain the architecture and operation below.

PRELAB:  Answer question Q1-Q4 given below.

SPECIFICATIONS:

The nanoprocessor to be designed is shown in Fig. 1. The instruction to be executed  and the data to be processed are specified  using fourteen toggle switches on the Altera DE board.  To execute a specific instruction, the binary patterns corresponding to the instruction  Inst[3...0],  any associated Register  Reg[1..0], and any required data  Data[3...0] are  provided via these toggle switches. As the number of  switches on DE0 and DE-10 lite boards are insufficient, please ground the last four bits DATA[7..4] as in the  previous labs. The data bus will still be 8-bits corresponding to Data[7..0]. The complete instruction set is specified elsewhere in this document. 

Example A: For the instruction  IN R1,5   the first four switches (Inst[3..0])  identify it to be the "IN" instruction, next two switches (Reg[1..0]) are 01 corresponding to register R1, and the last four switches (Data[3..0]) are set to 00000101 corresponding to 5.   Let  '1111'  be the  four bit pattern, commonly referred to as the machine code (MC), to specify the IN instruction.   Thus the toggle switch values are '1111 01 0101'.

Q1: What are the toggle switch values for Example B?  Assume the MC for OUT instruction to be 1110. Data values are not used thus they are don't cares.

Application of a clock pulse using a push-button switch causes the instruction to be carried out.  Instructions that display a result, will display the value on the Seven Segment Display unit.  Thus a program execution consists of applying a sequence of binary patterns corresponding to each instruction followed by a clock.

IMPLEMENTATION:

Figure 2 illustrates the architecture of the nanoprocessor.  It consists of the following components that operate on data (called data path):

1. Three 8-bit registers: R1, R2 and R3
2. An Accumulator (denoted by A). This is an 8-bit register that has a special role in that one operand for addition and multiplication operation is always in the accumulator.
3. An Adder/Subtractor unit
4. A Multiplier unit
5. A 3-character 7-segment Display Unit
6. A Control Unit  that generates the different control signals.
   

Take a careful look at each of these components  and how they are interconnected. Notice that you have already completed the Adder/Subtractor, the Multiplier, the Display Unit and the Register bank. The ALU is slightly more complicated than the Tally Unit. 

The Control Logic Circuit (Control Unit in  Figure 2, implemented using a ROM) generates the control signals C[10...0] to carry out a given operation.  
Recall from previous labs that signals DE1, DE2, etc. indicate that the corresponding register is enabled for latching data upon the clock edge, while OE1, OE2, etc., enable the tri-state buffers built into the corresponding registers.

Example A:  Consider the toggle switches  set to the pattern for  IN R1,5 as stated above.   The question is how to make the circuit carry out this instruction.
Suppose the control unit sets  all the control signals to 0  except for C0, C7. Note that the connections to EN of Register_Select are inverted, i.e., C7' and C8'.
As C0 is 1, pattern on Data[7...0], which corresponds to 5  appears on data bus.
As C7 is 1,  and Reg[1...0] is 01,   DE1 becomes 1. 
When the clock is applied, data on data bus is thus latched to R1.  None of the other registers change as their DE signals are 0. 
Thus to carry out IN R1, data  instruction, the control unit needs to set C0, C7 to 1 and remaining signals to 0. 
More specifically, when  Instru[3...0] = 1111,    C[10...0] = 00010000001.

Q2:  Find the control signal values for Example B. 
Q3:  What control signals have to be activated to display the contents of A ?  We will call this OUTA instruction.

The Control Unit shown in Figure 2 responsible for generating C[10...0] for a given MC Inst[3...0].  It can easily be implemented using a ROM as shown in Figure 3. As the number of switches on DE0  and DE10-Lite boards are insufficient,  ground the last four bits Data[7..4] as in previous labs.

                        

Opcode	Operand	Operation performed
IN	Reg, (value)	Load a value from keypad into a specified register (Reg)
INA	(value)	Load  a value from keypad to the Accumulator (A)
OUT	Reg	Display the value in Reg
OUTA		Display the value in the Accumulator
ADD	Reg	Add values in A and in Reg and store the result in A
SUB	Reg	Subtract value in Reg from the value in A and store the result in A
MUL	Reg	Multiply values in A and Reg and store the result in  A   (Note: As the multiplier is a 4-bit multiplier, only the first 4 bits of each input   are used in the multiplier for processing, i.e., data from A[3..0] and Reg[3..0] lines are used as inputs to the multiplier)
MOV	Reg	Move (i.e., copy)  the  value in Reg to A
MOVA	Reg	Move the  value in A to Reg

              

Use 10 bits to specify a single instruction as follows:
          4 bits for the operation (Op-code)
          2 bits for the register Reg[1..0]
          4 bits for data

The binary codes (also called opcodes) for the different instructions are as follows:

Registers are identified using the following binary codes using the Register Bank:
   R1 - 01
   R2 - 10
   R3 - 11

 PROCEDURE:

1. Prepare a table of contents for control ROM
2. Design the circuit.
     Notes:

• Use the 10 toggle switches on the Altera DE0 board to specify each instruction
• Make use of the device available in Quartus II libraries
• Reuse the different modules you designed for previous labs as follows:
•  TriState Buffer Array [TSBA] - Lab 9
•   Register bank - Lab 9 part 1
  
•   Accumulator - register designed in Lab 9
•   Control ROM - Refer to Lab 7 for creating a new ROM. The Control ROM has 4 input bits (instruction) and 11 output bits, thus use for the ROM size: WIDTH=16, DEPTH=16
• Once the instruction is set on toggle switches,  a clock pulse is applied to execute the instruction

3. Verify its operations for a small set of instructions.

Example:
   IN  R1,3
   IN  R2,5
   OUT R1
   OUT R2
   MOV R1
   ADD R2
   OUTA

4. Demonstrate your circuit using the  test program given below. 

IN R3, 4     (Enter 4 on keypad and store it in  register R3)

OUT  R3    (Display value stored in  R3)

IN R2, 2     (Store 2 in R2)

OUT  R2    (Display value in R2)

IN R1, 5     (Store 5 in  R1)

OUT  R1    (Display value stored in R1)

MOV R1    (Move value in register R1 to A)

ADD R2     (Add A and R2 and store result in A)

OUTA         (Display the result in A)

SUB R2     (Subtract the value in R2 from A)

OUTA         (Display result in A)

MUL R3     (Multiply contents in A and R3 and store result in A)

OUTA         (Display result)

MOVA R1  (Move value in A to register R1)

OUT R1      (Display value stored in R1)

6. Come up with a new instruction for the processor.

7. If you have time, use the following procedure to find the sum of the first N integers:

Program to add first N integers: 

1+2+...+(N-1)+N

Following code is the initialization.

IN     R1,0
IN     R2,(value of N)
IN     R3,1

Repeat the following code until display becomes 0.

MOV    R2
ADD     R1
MOVA  R1
MOV    R2
SUB     R3
MOVA  R2
OUT     R2

Following code will display the result.

        MOV R1
       OUTA

© 2025. Anura Jayasumana, Colorado State University.   This work is openly licensed via  CC BY
last modified:  01/30/2025