The Challenge
The fully
digital Silver Cloud was a smashing success, and Banana
Electronics has decided to embark on a nanoprocessor
design. Examples of programmable processors include
microprocessors in your computer. Your task is to design a
nanoprocessor that can execute simple programs. You have already
designed many of the modules required in previous projects,
e.g., adder/subtractor, multiplier, register bank and ROM
based SSD decoder, which will be reused in this design.
After completion of the design, establish the functionality of
your design through simulation and hardware implementation.
This is your last official Banana project, so this is your last
opportunity to prepare an excellent report as explained in another
link of this website.
BACKGROUND:
A microprocessor is the core functional unit
(often called the brain) of any computer. They are also
widely used in many processing devices, appliances, automobiles,
etc. A microprocessor is a programmable device that executes
sets of instructions (software). A program consists
of a sequence of instructions that the microprocessor carries out.
Each instruction corresponds to a simple operation such as
addition, multiplication or data movement.
Example A: The instruction IN R1,5
causes microprocessor to load the value '5' into
register R1
Example B: The instruction OUT R2
to displays the value in register R2 on the seven-segment display.
Using a series of such instructions
more complex computations can be carried out.
You will be designing a very simple processor (ECE102
nanoprocessor) capable of carrying out a small set of
instructions.
Examples A and B above will be used to explain the architecture
and operation below.
PRELAB: Answer question Q1-Q4 given below.
SPECIFICATIONS:
The nanoprocessor to be designed is shown in Fig. 1. The
instruction to be executed and the data to be processed are
specified using fourteen toggle switches on the Altera DE
board. To execute a specific instruction, the binary
patterns corresponding to the instruction Inst[3...0],
any associated Register Reg[1..0], and any required
data Data[7...0] are provided via these toggle
switches. The complete instruction set is specified
elsewhere in this document.
Example A: For the
instruction IN R1,5
the first four switches will identify it to be the "IN"
instruction, next two switches will be 01 corresponding to
register R1, and the last four switches will be set to 00000101
corresponding to 5. Let '1111' be
the four bit pattern, commonly referred to as the machine
code (MC), to specify the IN instruction. Thus the
toggle switch values are '1111 01 00000101'.
Q1: What are
the toggle switch values for Example B? Assume the MC for OUT instruction to be 1110. Data values are
not used thus they are don't cares.
Application of a
clock pulse using a push-button switch causes the instruction to
be carried out. Instructions that display a result, will
display the value on the Seven Segment Display unit. Thus a
program execution consists of applying a sequence of binary
patterns corresponding to each instruction followed by a clock.
IMPLEMENTATION:
Figure 2 illustrates
the architecture of the nanoprocessor. It consists of the
following components that operate on data (called data path):
Take a careful look
at each of these components and how they are interconnected.
Notice that you have already completed the Adder/Subtractor, the
Multiplier, the Display Unit and the Register bank. The ALU is
slightly more complicated than the Tally Unit.
A Control Logic
Circuit generates the control signals C[10...0] to
carry out a given operation.
Recall from previous labs that signals DE1, DE2, etc. indicate
that the corresponding register is enabled for latching data upon
the clock edge, while OE1, OE2, etc., enable the tri-state buffer
built into the corresponding register.
Example A:
Suppose the toggle switches are specified for IN
R1,5 as stated earlier. The question is how
to make the circuit carry out this instruction.
Suppose the control unit sets all the control signals to
0 except for C0, C7 which are set to 1.
As C0 is 1, pattern on Data[7...0], which corresponds to
5 appears on data bus.
As C7 is 1, and Reg[1...0] is 01, DE1
becomes 1.
When the clock is applied, data on data bus is thus latched to
R1. None of the other registers change as their DE signals
are 0.
Thus to carry out IN R1, data instruction, the control unit
needs to set C0, C7 to 1 and remaining signals to 0.
More specifically, when Inst[3...0] =
1111, C[8...0] = 010000010.
Q2:
Find the control signal values for Example B.
Q3: What control signals have to be activated to
display the contents of A ? We will call this OUTA instruction.
The Control Unit shown in Figure 2 responsible for generating C[8...0] for a given MC Inst[3...0]. It can easily be implemented using a ROM as shown in Figure 3.
Opcode
Operand
Operation performed
IN
Reg, (value)
Load a value from keypad into a specified
register
INA
vaue
Load a value from keypad to
the Accumulator (A)
OUT
Reg
Display value in the specified register
OUTA
Display value in the Accumulator
ADD
Reg
Add value in A and specified register and store the result in A
SUB
Reg
Subtract value in specified register from the value in A
MUL
Reg
Multiply value in A and value in specified register and store the
result in A (NOTE: As the multiplier is a 4-bit
multiplier, only the first 4 bits of each input
are used in the
multiplier for processing i.e. data from A[3..0] and Reg[3..0]
lines will be used as inputs to the multiplier)
MOV Reg
Move (i.e., copy) the value in
specified register to A
MOVA Reg
Move the value in A to specified
register
Use 16 bits to specify a single
instruction as follows:
4 bits for
the operation (Op-code)
2 bits for
the register Reg[1..0]
8 bits for
data
The binary codes for different
instructions are as follows:
IN 1111
INA 1110
OUT 1011
OUTA 1010
MOV 0011
MOVA 0010
ADD 0101
SUB 0110
MUL 0111
Registers are identified using the
following binary codes using the Register Bank:
R1- 01
R2 - 10
R3 - 11
PROCEDURE:
1. Prepare a table of contents for control ROM
2. Design the circuit.
Notes:
- Use the 16 toggle switches on the Altera DE board to specify each instruction
- Make use of the device available in Quartus II libraries
- Reuse the different modules you designed for previous labs as follows:
- TriState Buffer Array [TSBA] - Lab 9
- Register bank - Lab 9 part 2
- Accumulator - register designed in Lab 9
- Control ROM - Refer to Lab 7 for creating a ROM. The Control ROM has 4 input bits (instruction) and 11 output bits, thus use for the ROM size: WIDTH=16, DEPTH=16
- Once the instruction is set on toggle switches, a clock pulse is applied to execute the instruction
3. Verify its operations for a small set of instructions.
Example:
IN R1,3
IN R2,5
OUT R1
OUT R2
MOV R1
ADD R2
OUTA
4. Demonstrate your circuit using following test program.
All the instructions will be tested on the DE board during the demo.
6. Come up with a new instruction for the processor.
7. If you have time, use the
following procedure to find the sum of first N integers:
Program to add first N integers:
1+2+...+(N-1)+NFollowing code is the initialization.
IN R1,0
IN R2,(value of N)
IN R3,1
Repeat the following code until display becomes 0.
ADD R1,R2
SUB
OUT R2
Following code will display the result.
OUTA