Project 5:
The Challenge


Design and implement a 4-bit multiplier.
Integrate the adder/subtractor  from Project 4  and the multiplier units to form a simple Arithmetic Logic Unit (ALU)  that accepts two 8-bit binary integers as inputs and produces an 8-bit output consisting of sum, difference or the product. Implement, and test the ALU
Design:

                                                                              ALU block diagram
                                                 Figure 1: ALU Block Schematic Diagram                                                                                         



tsba
                                              Figure 2: Tri-State Buffer Array

A TSBA (Figure 6) is used to allow or restrict data flow through a data line/ bus. The above figure will explain the circuit of a Tri-state Buffer Array.


 Procedure:
    1. The input variables are 8-bit binary numbers (A[7..0]) and (B[7..0]) generated using switches 0-6  and 7-14 on your DE board: SW0 = A0,..SW8=B0.  Result will be displayed using the LEDs of  DE-2 board. The following figure will help you understand how to name the bus-node/ node-bus connections in Quartus.                                                                                                                                                                    bus naming
      2.                                    Figure 3: Naming bus-Node transition in Quartus
    2. Develop a 4-bit array multiplier design using Full Adders and logic gates. Use A[3..0] and B[3..0] as data input lines for multiplier block.
    3. Save multipler design as a symbol "Multiplier.bsf"
    4. You can use the adder/ Subtractor from Lab 4 as a block.
    5. The Function selector decides whether we are using multiplier block or adder/ subtractor block for processing out input data. Use SW17 for this.
    6. The add/sub control decides whether you want to add or subtract. Use SW16 for this.
    7. Using Quartus-II  create the  schematic, simulate and verify your implementation.  Show results for at least 6 different input combinations. (2 for multiplier, 2 for adder, and 2 for subtractor)
    8. Implement this hardware on your DE-2 Board and test it.
    9. Strictly for extra credit [not required]: Design and test an 8 by 8 multiplier.

Report:
Prepare a memorandum which is addressed to the manager of the R&D group at Banana. Go to the Preparing the Memo link to review the general requirements for Banana Memos or to the What to Include and Grading Policy link for the specific things to include in the Project #5 report.

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