Lab Assignments

Lab sections meet in Room C207 Engineering. Labs start on Monday August 26th, 2019.

Policies:

• Lab attendance: Mandatory. In rare situations when you cannot attend the your scheduled  lab session due to circumstances beyond your control, you must obtain clearance in advance from your lab instructor. In such a case you must attend another lab section during that same week. Failing that, you will be marked absent for the project and will receive a zero score. Remember that all projects must be completed with a passing grade in order to pass the course.

• Conduct in the lab: Students are expected to maintain a professional working atmosphere in the lab, which includes not disturbing others, not talking loud, and following  instructions provided by the Teaching Assistants. Use of cellphones (for voice or texting) is not allowed. No food or drinks allowed in C207.

• Prelab: Prelabs must be ready by the beginning of each lab session.
  

• Submissions: Each lab consists of one or more submissions and/or demonstrations.
     1. Prelab – A set of questions that need to be completed before you start the lab session.
     2. Demo - Demonstration of the completed lab on DE0/ DE1 / DE2 hardware
     3. Lab report – A softcopy of the typed summary of the work done for the lab accommodating theory, technical details, circuits, and results.
     
• Prelabs are due before the start of the lab and must be submitted on-line via Canvas. Submit your prelab with the lab report.   
  
• Lab reports are to be submitted online via Canvas unless otherwise indicated before the start of the next lab session.
     You may do the hardware demo to any TA or LA anytime before the start date of the next project for your lab section (during GTA's office hours or during other lab sections).  At the time of the demo, you must be able to answer TA's questions related to the lab. Lab instructor will mark the completion of your  demo once she/he has seen your hardware circuit working correctly. A soft copy of the lab report must be submitted after a successful demonstration. Demonstrating your hardware circuit during the next lab meeting is permitted, but make sure that it works flawlessly. You will not be given extra time to debug your circuit at that time. No excuses will be entertained in this regard.

• Policy on collaboration with other students: Design alone, build alone, write alone, and submit individually prepared reports and circuits. It's okay to talk about the assignment, give advice, receive advice, but do your own work.

• Grading policy: The grading differs from one project to the other.  An example would be: hardware circuit: 30%, required technical items in the report: 40%, memo text: 20%, instructor discretion: 10%.  A neatness bonus of 5% may be assigned.

• Penalties: Penalties will be assessed for each lab as follows:  lateness per day: -10%, and not following Banana memo format: -10%.

• Demonstration for online students: Online students are expected to  demonstrate each lab via a video call. Set up an appointment for each lab  with your Graduate Teaching Assistant. To respect everyone's time, make sure your circuit is ready for demo before you start the video call.

All submitted work should be your own. Copying of language, structure, images, ideas, or thoughts of another, and representing them as one’s own without proper acknowledgement (from web sites, books, papers, other students, solutions from previous offerings of this course, etc.) and failure to cite sources properly is not acceptable. Sources must always be appropriately referenced, whether the source is printed, electronic, or spoken.

Assignments & Instructions:

• It is essential to read the assignment before the lab and be ready to begin when you come to the lab.
• Report is due in a week.
   

Week	Lab   number	Project Description
August 26 - August 30	0	Introduction  Creating an Engineering Network Account
Sept 3 - Sept 9	1	Introduction to Altera DE board and Quartus II Design Software       Lab 1 Circuit      Lab steps     DE0 manual The only difference between DE0, DE1 and DE2 implementation is the FPGA number and PIN assignments. (Quartus II) software instructions remain the same.
Sept 10 - Sept 16	2	Schematic Entry, Timing Diagrams and Functional Simulation using Quartus II
Sept 17 - Sept 23	3	Design, Simulation and Verification of Combinational Circuits
Sept 24 - Sept 30	4	Two's Complement Adder Subtractor Design
Oct 1 - Oct 7	5	The Arithmatic Logic Unit
Oct 8 - Oct 14	6	The Seven Segment Display
Oct 15 - Oct 21	7	Binary to Seven Segment Decoder
Oct 22 - Oct 28	8	An Accumulation based Tally Unit
Oct 29 - Nov 1		This is a make-up week.  Any late labs have to be completed and reports must be submitted during this week. There will not be another opportunity to complete labs 1-7 after this.  TAs/ LAs will not accept any demos or reports for Labs 1-7 after this week. Any incomplete lab will automatically result in an "F" for the course as stated in the outline. Lab 9 will be conducted from Monday, Nov 4th.
Nov 4 - Nov 8	9	Shift Register and Register Bank
Nov 11 - Nov 15	10	Design of Counters
Nov 18 - Nov 22	11	An Encryption Unit for Serial Communication
Nov 25 - Nov 29		Fall break!
Dec 2 - Dec 6	12	Nanoprocessor
Dec 2 - Dec 13	13	Verilog

• The lab assignments use Altera DE0, DE1, or DE2 boards and Quartus II software, available in C207 Engr.

Downloads:

• Quartus II software is available for download and installation on your computer (See Quartus II 9.1 Web Edition or 18.1 Lite Edition Software).