Syllabus - Fall 2017 

Objectives: To understand the concepts of digital logic and learn methods and tools for the design of digital circuits.

Prerequisites: Major in ECE or prior approval

URL: The official home page for ECE102 is located at                                   
                                       www.engr.colostate.edu/ECE102/FALL17 
Students are expected to visit the official home page frequently for class handouts, homework assignments, lab assignments, and important announcements!

Grading Policy: The grade will be based on quizzes & homework (20%), labs (20%), midterm 1 (15%), midterm 2 (15%), midterm 3 (15%), and the final exam (15%).
The +/- grading scheme will be used, with the scale
                            >90% -- A, A+ 
                            >80% -- B, B+, A-
                            >70% -- C, C+, B-
                            >60% -- D
You must pass EVERY lab assignment (score > 60%) in order to pass the course. A bonus not exceeding 5% will be awarded for neatness and clarity of presentation on some of your graded work.

Short Quizzes: On-line quizzes will be posted on canvas.  They will demand a current familiarity with the course material.

Homework Procedures: Homework assignments are due in the drop-box in Engineering B106. To facilitate returning your graded homework to you, write your lab section number in the upper right corner of the first page. Selected questions from each homework assignment will be graded. However, turn in all of the assigned problems. All assigned problems are equally important for the development of your understanding of the subjects of digital logic. To receive full credit for your homework, show all reasonable steps in solving the problem. Written solutions will be available in the lab after the due date of the homework.

Late Policy: Quizzes and Exams must be taken as scheduled in order to receive credit. Late homework will not be accepted unless its lateness is due to circumstances beyond your control. To receive full credit, lab reports must be turned in to the Graduate Teaching Assistant in the lab on the date due. Late lab reports will be accepted, but points will be deducted from the score.

Lab Assignments:  Laboratory assignments are a very important component of this course. You will learn to design and develop digital logic circuits, and by the end of the semester will be able to design sophisticated digital circuits.  We use a set of digital tools used by professional engineers, which may appear a bit intimidating at first. After the first two to three labs,  you will become comfortable with the tools and will be on your way to designing some interesting circuits.

Conduct and Nature of Exams: You will be allowed to use one double-sided page of notes, prepared by you, during the four exams. Exams will be straightforward, but will demand the kind of preparation only possible through continual, daily study.

Instructional Objectives: Given during class, these are the bases of all quiz and exam questions, and homework assignments. For this reason, consistent class attendance is very important.

Textbook: Fundamentals of Logic Design, by Charles H. Roth published by Cengage Learning. 
                      The latest is the 7th Edition.  Sixth,  fifth or fourth editions are acceptable.
                      Some of these earlier  editions were  published by Thompson Publishing Co.
                      Be aware that there are differences in chapter,   page and problem numbers of the
                      different editions.  CSU Bookstore carries a paperback version  containing the necessary chapters
                      of the 7th edition at a lower price  compared to the regular version.
                      It is not critical to have the text during the first week.

Tutoring: The course's Graduate Teaching Assistants will be available for drop-in consultation as well as help sessions at times and places listed on the website.

Topics:

Introduction to Digital Systems, Number systems      Chapter 1
Boolean Algebra                                                                     Chapter 2
Algebraic simplification                                                       Chapter 3
Minterm and maxterm expansions                                  Chapter 4
Karnaugh maps                                                                      Chapter 5
Multi-level gate networks                                                   Chapter 7
Combinational network design                                         Chapter 8
Multiplexers, decoders and PLD's                                    Chapter 9
Latches and Flip-flops                                                          Chapter 11
Counters and sequential networks                                  Chapter 12
Analysis of synchronous sequential networks             Chapter 13
State graphs and tables                                                        Chapter 14
Reduction of state tables/state assignment                  Chapter 15
Sequential Network Design                                                Chapter 16

Academic Integrity: This course will adhere to the CSU Academic Integrity Policy as found in the General Catalog 
( http://www.conflictresolution.colostate.edu/academic-integrity ) and the Student Conduct Code ( http://www.conflictresolution.colostate.edu/conduct-code ). At a minimum, violations will result in a grading penalty in this course and a report to the Office of Conflict Resolution and Student Conduct Services.