ECE102             Digital Logic Design                                Fall 2017

                                Objectives for Final Exam

Do the sample exams available on the web. 
You are allowed to bring one page (2-sided) of information.
The emphasis of the exam will be on the highlighted objectives. However, you are
expected to have a working knowledge of all the objectives.
 
 Binary Representation

State the differences between digital and analog systems
Define the term `positional number system'
Represent numbers in decimal, binary, octal and hexadecimal notations and
convert from one notation to the other
Add, subtract, multiply and divide binary numbers
Represent numbers in sign-magnitude, one's complement and two's complement forms
Carry out addition and subtraction, and identify overflow conditions
Represent numbers in binary coded decimal format (BCD)
Represent characters using ASCII format
 Represent voice, images, etc. in binary

Combinational Logic

Define the basic logic operations (AND, OR, NOT, NAND, NOR, XOR)
Evaluate Boolean expressions
Derive the logic function implemented by a logic circuit
Use Laws and Theorems of Boolean Algebra to simplify logic expressions
Implement Boolean expressions  using 2-level networks (SOP, POS)
Find the complement of a  Boolean expression using DeMorgan's Law
Find the dual of a  Boolean expression
State and use the Negative Logic Theorem
Describe the advantages of using NOR and NAND gates compared to AND and OR
gates
Use Consensus theorem to simplify logic expressions
Convert functional specifications  (written in English)  to logic expressions
Convert specifications written in English to a truth table
Obtain minterm and maxterm expansions (using m/M notations or in algebraic form)
                                                                  from a truth table or an algebraic expression
 Convert a  minterm expansion it a  maxterm expansion and vise versa
Use m/M notation to obtain product/sum of logic expressions
 Use don't care terms to simplify logic expressions

Represent 2,3,4,5 and 6 variable functions using Karnaugh maps
Represent expressions given in SOP, POS, maxterm or minterm form on K-map
Obtain minimum POS and SOP expansions using K-map

Derive alternative gate symbols for basic logic gates
Implement logic functions using basic 2-level forms
Convert networks from one form to another
Implement logic functions using only NOR gates or only NAND gates
Implement logic functions using multilevel networks
Design multiple-output circuits
Implement combinational logic expressions using multiplexers, demultiplexers, ROMs and programmable logic


Arithmetic Circuits
 Design logic circuits to add/subtract two's complement numbers
Design array multiplier circuits

Tri-state Circuits
Use tri-state logic gates to design a bus interconnecting a set of registers.  


Sequential Circuits  (At least 60% of the exam will deal with following objectives)

Describe the operation of S-R, T, D, and J-K latches and flip-flops
Draw timing diagrams of circuits containing latches and flip-flops
Draw the circuit diagram, and describe the operation of  a shift register and a cyclic shift register
Design counters using T, D, S-R and J-K flip-flops (use tables and/or maps)
Analyze Moore  type and Mealy sequential  networks:
    - Derive the state graphs state tables of a given sequential circuit
    - Draw timing diagrams corresponding to a given set of input wave forms
Derive Moore and Mealy type state graphs to meet given specifications
Synthesize Moore and Mealy type networks to meet given specifications
 Identify equivalent states of a state graph and reduce the state graph
 Determine whether two given state graphs are equivalent

 
 


12/02/2017