ECE 102 - Homework 8
Due 10/26/2017
1. Consider the
function F =
(A'+B+C')(B'+C+D')(A+B+C+D)(A'+B'+C'+D')(A+B+C')
a) Derive the minimum POS and draw the
minimum 2-level OR-AND implementation,
b) Manipulate the minimum POS algebraically to
obtain and draw the minimum 2-level NOR-NOR, AND-NOR
and NAND-AND realizations,
c) Draw the minimum 2-level AND-OR implementation
of F,
d) Manipulate the expression above algebraically
and obtain the NAND-NAND, OR-NAND and OR-NOR implementations.
2. a) Realize F = P'Q'R'+ P'S'+RS using only
2-input NAND gates,
b) Realize X = PT+QST+QRTU using only
2-input NOR gates.
3. Convert the following circuits to all NAND gates:
4. Complete the timing diagram for the output Q of a flip-flop
for each of the following cases.
Assume the initial value of Q to be 0, and that the delay
of the device is much smaller than
the clock period given:
a) A
gated D-latch ( with CLK signal connected to the gate
input),
b) A positive
edge-triggered D flip-flop,
c) A negative edge
triggered D flip-flop.
5. Complete the timing diagrams for
a) a negative edge-triggered J-K flip-flop, and b) a
positive-edge triggered J-K flip-flop. Assume initial output to
be 1.
6. Complete the timing diagram assuming the
initial value of the outputs (at t=0)
of the T flip-flops to be 0's. This circuit
is called a 'ripple counter.' Why?
7. Complete the timing diagram for the given
circuit depicting B,C,D and E. What is the function of
this circuit.
Follow the guidelines for preparing homework
solutions.
Turn in solutions to all the problems. Only a subset
of the problems will be graded. Points will be taken off for
problems not submitted.