The Challenge

Your next assignment at Banana is to design and build a tally unit that displays the total number of eBananas sold each day. When a shipment of eBananas leaves the company, the number of eBananas will be added to the number on the display. Occasionally a shipment is returned, in which case the corresponding number is subtracted.

Specifications:

You have been asked to build a register and an arithmetic unit to perform following fundamental operations with the register, such as, adding to and subtracting numbers from the register, accumulating the result in the register. Design will use the  adder/subtracter logic and the binary to seven segment display units that you have already designed. You will build a register and integrate all the units to build the tally unit as indicated in Figure 1.
The value to be displayed is expected to be a positive integer. Note that the adder/subtracter unit designed was for 8-bit two's complement numbers; however, we can still use it for positive integer arithmetic because two's complement of a positive number is the same number.

Register:
Design a negative edge-triggered 8-bit register using D flip-flops. The register will have an asynchronous CLEAR input that allows its contents to set to zero.

Tally Unit: 

The register, called A, has capacity of 8 bits, denoted as  A₇-A₀. A₇ holds the most significant bit of data while A₀ holds the least significant bit of data. In the previous project, you designed an 8-bit full adder/subtracter, which can be used to add or subtract data.
One of the inputs to the adder comes from a set of 5 switches on the Altera board which will be controlled by you. Set the three most significant bits to zero. The other input to the adder/subtractor is from register A. The output of the adder replaces the data in A. This capability is called “accumulation”. The register A thus will contain a running tally of the total.

Figure 1.  Schematic diagram of accumulator based tally unit

Details:  

• The register contents are displayed on 3 seven-segment displays.
  
• The external input to the adder is from switches SW4-SW0. There are more register bits than input data bits so as to allow for accumulation of numbers larger than can be represented by 5 bits.
• SW17:  0 => addition; 1 => subtraction.
• KEY0 is used to generate the clock manually, i.e., each time it is pressed, another addition or subtraction will occur and the result will be displayed.
  
• KEY1 clears register A.
• As the seven segment display needs to display the current tally all the time, use a faster clock available on the DE-2 board to read the ROM and update the display. Assign PIN_N2, which has a clock frequency of 50MHz, to clock the ROM.
  

• Verify your implementation by applying different input combinations. Your report will include functional simulation timing diagrams for
  the circuit (excluding binary to seven-segment decoder and display) adding not less than three different numbers followed by subtraction of one number.
  
• Implement your design on the DE-2 board and demonstrate your design in hardware at the next group meeting.

Extra Credit:
Once the result exceeds 255 or becomes negative, the display will not accurately reflect the tally of eBananas. Design and implement an addition to the circuit that indicates on LED7 that the tally has exceeded 255 and on LED6 that the tally has become negative. Once either LED comes on, it should remain lit until the CLEAR button is pressed.

 

REPORT

Prepare a professional memorandum addressed to the manager of the R&D group at Banana. Go to the Preparing the Memo link to review the general requirements for Banana Memos or to the What to Include in Report #8  link for the specific things to include in the Project #8 report.