Key: $rd Instr[15:11] $rs Instr[25:21] $rt Instr[20:16] Imm5 5-bit signed immediate Imm5u 5-bit unsigned immediate Imm16 16-bit signed immediate Imm16u 16-bit unsigned immediate Selected Basic Integer Arithmetic Instructions ------------------------------------------------------------------------------------------------------- add $rd,$rs,$rt Addition with overflow GPR[rd] <-- GPR[rs] + GPR[rt] addu $rd,$rs,$rt Addition "unsigned" without overflow GPR[rd] <-- GPR[rs] + GPR[rt] addi $rt,$rs,Imm16 Addition immediate with overflow GPR[rt] <-- GPR[rs] + Imm16 addiu $rt,$rs,Imm16 Addition immediate "unsigned" without overflow GPR[rt] <-- GPR[rs] + Imm16 div $rs,$rt Division with overflow $lo <-- GPR[rs]/GPR[rt] $hi <-- GPR[rs]%GPR[rt] divu $rs,$rt Division "unsigned" without overflow $lo <-- GPR[rs]/GPR[rt] $hi <-- GPR[rs]%GPR[rt] mul $rd,$rs,$rt Multiplication without overflow GPR[rd] <-- (GPR[rs]*GPR[rt])[31:0] mult $rs,$rt Multiplication without overflow $hi <-- (GPR[rs]*GPR[rt])[63:32] $lo <-- (GPR[rs]*GPR[rt])[31:0] multu $rs,$rt Multipication "unsigned" without overflow $hi <-- (GPR[rs]*GPR[rt])[63:32] $lo <-- (GPR[rs]*GPR[rt])[31:0] sub $rd,$rs,$rt Subtraction with overflow GPR[rd] <-- GPR[rs] - GPR[rt] subu $rd,$rs,$rt Subtraction unsigned without overflow GPR[rd] <-- GPR[rs] - GPR[rt] sra $rd,$rt,Imm5u Shift right arithmetic (with sign-extension) GPR[rd] <-- GPR[rt] >> Imm5u srav $rd,$rt,$rs Shift right arithmetic variable (with sign-extension) GPR[rd] <-- GPR[rt] >> GPR[rs] Selected Basic Logic Instructions ------------------------------------------------------------------------------------------------------- and $rd,$rs,$rt Bitwise AND GPR[rd[i]] <-- GPR[rs[i]] & GPR[rt[i]], i = 0..31 andi $1,$2,Imm16u Bitwise AND immediate (immediate is zero-extended) GPR[rd[i]] <-- GPR[rs[i]] & $Imm16u[i], i = 0..31 nor $1,$2,$3 Bitwise NOR GPR[rd[i]] <-- !(GPR[rs[i]] | GPR[rt[i]]), i = 0..31 or $1,$2,$3 Bitwise OR GPR[rd[i]] <-- GPR[rs[i]] | GPR[rt[i]], i = 0..31 ori $1,$2,Imm16u Bitwise OR immediate (immediate is zero-extended) GPR[rd[i]] <-- GPR[rs[i]] | $Imm16u[i], i = 0..31 xor $1,$2,$3 Bitwise XOR (exclusive OR) GPR[rd[i]] <-- GPR[rs[i]] ^ GPR[rt[i]], i = 0..31 xori $1,$2,Imm16u Bitwise XOR immediate (immediate is zero-extended) GPR[rd[i]] <-- GPR[rs[i]] ^ $Imm16u[i], i = 0..31 sll $rd,$rt,Imm5u Shift left logical GPR[$rd] <-- GPR[$rt] << Imm5u sllv $rd,$rt,$rs Shift left logical variable GPR[rd] <-- GPR[rt] << GPR[rs] srl $rd,$rt,Imm5u Shift right logical (no sign-extension) GPR[rd] <-- GPR[rt] >> Imm5u srlv $rd,$rt,$rs Shift right logical variable (no sign-extension) GPR[rd] <-- GPR[rt] >> GPR[rs] slt $rd,$rs,$rt Set less than GPR[rd] <-- (GPR[rs] < GPR[rt]) slti $rd,$rs,Imm16 Set less than immediate Selected Basic Control-of-flow Instructions ------------------------------------------------------------------------------------------------------- beq $1,$2,label Branch if equal bgez $1,label Branch if greater than or equal to zero bgtz $1,label Branch if greater than zero blez $1,label Branch if less than or equal to zero bltz $1,label Branch if less than zero bne $1,$2,label Branch if not equal break Break execution j target Jump unconditionally jal target Jump and link (puts return address in $ra) jalr $1 Jump and link register (puts return address in $ra) jalr $1,$2 Jump and link register (puts return address in first operand) jr $1 Jump register unconditionally Basic Data Transfer Instructions ------------------------------------------------------------------------------------------------------- lb $1,Imm16($2) Load byte lbu $1,Imm16($2) Load byte unaligned lh $1,Imm16($2) Load halfword lhu $1,Imm16($2) Load halfword unaligned ll $1,Imm16($2) Load linked lui $1,100 Load upper immediate lw $1,Imm16($2) Load word lwl $1,Imm16($2) Load word left lwr $1,Imm16($2) Load word right mfhi $1 Move from HI register mflo $1 Move from LO register movn $1,$2,$3 Move conditional not zero movz $1,$2,$3 Move conditional zero mthi $1 Move to HI register mtlo $1 Move to LO register sb $1,Imm16($2) Store byte sc $1,Imm16($2) Store conditional sh $1,Imm16($2) Store halfword sw $1,Imm16($2) Store word swl $1,Imm16($2) Store word left swr $1,Imm16($2) Store word right Miscellaneous Basic Instructions ------------------------------------------------------------------------------------------------------- clo $1,$2 Count number of leading ones clz $1,$2 Count number of leading zeroes nop Null operation syscall Issue a system call Basic Exception-related Instructions ------------------------------------------------------------------------------------------------------- teq $1,$2 Trap if register contents are equal teqi $1,Imm16 Trap if register contents equal to immediate tge $1,$2 Trap if first register contents greater or equal tgei $1,Imm16 Trap if register contents greater than or equal to immediate tgeiu $1,Imm16 Trap if register contents greater or equal to immediate, unsigned tgeu $1,$2 Trap if first register contents greater or equal, unsigned tlt $1,$2 Trap if first register contents less tlti $1,Imm16 Trap if register contents less than immediate tltiu $1,Imm16 Trap if register contents less than immediate, unsigned tltu $1,$2 Trap if first register contents less, unsigned tne $1,$2 Trap if register contents are not equal tnei $1,Imm16 Trap if register contents not equal to immediate eret Exception return Basic Floating-point Arithmetic Instructions ------------------------------------------------------------------------------------------------------- abs.d $f2,$f4 Floating point absolute value double precision abs.s $f2,$f4 Floating point absolute value single precision add.d $f2,$f4,$f6 Floating point addition double precision add.s $f2,$f4,$f6 Floating point addition single precision div.d $f2,$f4,$f6 Floating point division double precision div.s $f2,$f4,$f6 Floating point division single precision c.eq.d $f2,$f4 Compare equal double precision, result in condition flag 0 c.eq.d 1,$f2,$f4 Compare equal double precision, result in specified condition flag c.eq.s $f2,$f4 Compare equal single precision, result in condition flag 0 c.eq.s 1,$f2,$f4 Compare equal single precision, result in specified condition flag c.le.d $f2,$f4 Compare less or equal double precision, result in condition flag 0 c.le.d 1,$f2,$f4 Compare less or equal double precision, result in specified condition flag c.le.s $f2,$f4 Compare less or equal single precision, result in condition flag 0 c.le.s 1,$f2,$f4 Compare less or equal single precision, result in specified condition flag c.lt.d $f2,$f4 Compare less than double precision, result in condition flag 0 c.lt.d 1,$f2,$f4 Compare less than double precision, result in specified condition flag c.lt.s $f2,$f4 Compare less than single precision, result in condition flag 0 c.lt.s 1,$f2,$f4 Compare less than single precision, result in specified condition flag ceil.w.d $f2,$f4 Ceiling double precision to word ceil.w.s $f2,$f4 Ceiling single precision to word cvt.d.s $f2,$f4 Convert from single precision to double precision cvt.d.w $f2,$f4 Convert from word to double precision cvt.s.d $f2,$f4 Convert from double precision to single precision cvt.s.w $f2,$f4 Convert from word to single precision cvt.w.d $f2,$f4 Convert from double precision to word cvt.w.s $f2,$f4 Convert from single precision to word floor.w.d $f2,$f4 Floor double precision to word floor.w.s $f2,$f4 Floor single precision to word ldc1 $f2,Imm16($2) Load double word Coprocessor 1 (FPU) lwc1 $f2,Imm16($2) Load word from Coprocessor 1 (FPU) mfc0 $1,$2 Move from Coprocessor 0 mfc1 $1,$f2 Move from Coprocessor 1 (FPU) mov.d $f2,$f4 Move floating point double precision mov.s $f2,$f4 Move floating point single precision movf $1,$2 Move if FP condition flag 0 false movf $1,$2,1 Move if specified FP condition flag false movf.d $f2,$f4 Move floating point double precision if condition flag 0 false movf.d $f2,$f4,1 Move floating point double precision if specified condition flag false movf.s $f2,$f4 Move floating point single precision if condition flag 0 false movf.s $f2,$f4,1 Move floating point double precision if specified condition flag false movn.d $f2,$f4,$3 Move floating point double precision if register not zero movn.s $f2,$f4,$3 Move floating point single precision if register not zero movt $1,$2 Move if FP condition flag 0 true movt $1,$2,1 Move if specfied FP condition flag true movt.d $f2,$f4 Move floating point double precision if condition flag 0 true movt.d $f2,$f4,1 Move floating point double precision if specified condition flag true movt.s $f2,$f4 Move floating point single precision if condition flag 0 true movt.s $f2,$f4,1 Move floating point single precision if specified condition flag true movz.d $f2,$f4,$3 Move floating point double precision if register zero movz.s $f2,$f4,$3 Move floating point single precision if register zero mtc0 $1,$2 Move to Coprocessor 0 mtc1 $1,$f2 Move to Coprocessor 1 (FPU) mul.d $f2,$f4,$f6 Floating point multiplication double precision mul.s $f2,$f4,$f6 Floating point multiplication single precision neg.d $f2,$f4 Floating point negate double precision neg.s $f2,$f4 Floating point negate single precision round.w.d $f2,$f4 Round double precision to word round.w.s $f2,$f4 Round single precision to word sdc1 $f2,Imm16($2) Store double word from Coprocessor 1 (FPU) sub.d $f2,$f4,$f6 Floating point subtraction double precision sub.s $f2,$f4,$f6 Floating point subtraction single precision sqrt.d $f2,$f4 Square root double precision sqrt.s $f2,$f4 Square root single precision swc1 $f2,Imm16($2) Store word from Coprocesor 1 (FPU) trunc.w.d $f2,$f4 Truncate double precision to word trunc.w.s $f2,$f4 Truncate single precision to word