Enabling high bandwidth and power-efficient communication between information processing cores in System-on-Chip (SoC) architectures is an essential but increasingly difficult aspect of electronic chip design. SoCs play a pivotal role in society today, as these application-specific high-performance VLSI circuits drive all major modern inventions including vehicles and airplanes, computers and phones, scientific and industrial infrastructure, as well as military systems. With SoC processing core counts increasing steadily every year to enable more sophisticated applications (e.g., high fidelity target discrimination, warfighter control and navigation), the demands of higher bandwidth and low latency transfers are putting greater pressure on SoC communication networks. The result is that chip power and performance are now dominated not by processor cores but by the network that transports data between processors and to memory. In other words, SoC robustness and quality is now network dominated.
The research objective of this project is to determine the best architectural modalities to insert silicon photonic interconnect technology into manycore electronic chips, in order to overcome performance and energy bottlenecks in today’s SoCs. The project involves creating performance, energy, and reliability models, along with innovative circuits, architectures, and optimization techniques, to expedite the deployment of silicon photonics into manycore SoCs in the near future, to overcome the severe shortcomings of electrical interconnects at the chip-scale (at the intra- and inter-chip levels). We are also working on designing photonics based accelerators for deep learning applications.
Selected Publications
E. Taheri, M. A. Mahdian, S. Pasricha, M. Nikdast, “TRINE: A Tree-Based Silicon Photonic Interposer Network for Energy-Efficient 2.5D Machine Learning Acceleration”, IEEE/ACM 16th International Workshop on Network on Chip Architectures (NoCArc), 2023.
F. Sunny, E. Taheri, M. Nikdast, S. Pasricha, “Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics”, IEEE/ACM DATE, 2023.
S. Pasricha, J. Jose, S. Deb, “Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures”, Vol. 39, Iss. 6, pp. 90-98, IEEE Design & Test, Dec 2022.
E. Taheri, S. Pasricha, M. Nikdast, “ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication”, IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2022.
A. Mirza, F. Sunny, P. Walsh, K. Hassan, S. Pasricha, M. Nikdast, “Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization under Fabrication-Process Variations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), 2022.
V. S. P. Karempudi, F. Sunny, I. Thakkar, M. Nikdast, and S. Pasricha, “Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study”, to appear, ACM Journal on Emerging Technologies in Computing Systems (JETC), 2022.
F. Sunny, A. Mirza, I. Thakkar, M. Nikdast, S. Pasricha, “ARXON: A Framework for Approximate Communication over Photonic Networks-on-Chip”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2021.
A. Mirza, S. Pasricha, and M. Nikdast, “Variation-Aware Inter-Device Matching in Silicon Photonic Microring Resonator Demultiplexers”, IEEE Photonics Conference (IPC), 2020.
A. Mirza, S. Avari, E. Taheri, S. Pasricha, and M. Nikdast, “Opportunities for cross-layer design in high-performance computing systems with integrated silicon photonic networks”, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, March 2020.
A. Mirza, F. Sunny, S. Pasricha, and M. Nikdast, “Silicon Photonic Microring Resonators: Design Optimization under Fabrication Non-uniformity“, IEEE/ACM Design, Automation and Test in Europe (DATE) Conference and Exhibition, March 2020.
F. Sunny, A. Mirza, I. Thakkar, S. Pasricha, and M. Nikdast, “LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020.
S. Pasricha, M. Nikdast, “A Survey of Silicon Photonics for Energy Efficient Manycore Computing” IEEE Design and Test, vol. 37, no. 4, pp. 60-81, Aug 2020.
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip“, IEEE Transactions on Multi-Scale Computing Systems (IEEE TMSCS), Vol. 4, No. 4, Oct-Dec 2018.
S. V. R. Chittamuru, D. Dharnidhar, S. Pasricha, R. Mahapatra “BiGNoC: Accelerating Big Data Computing with Application-Specific Photonic Network-on-Chip Architectures“, IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 29, Iss. 11, Nov 2018.
I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling,” IEEE Workshop on Energy-efficient Networks of Computers (E2NC): from the Chip to the Cloud, Oct 2018.
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2018.
S. Pasricha, S. V. R. Chittamuru, I. Thakkar, “Cross-Layer Thermal Reliability Management in Photonic Networks-on-Chip,” ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2018.
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “HYDRA: Heterodyne Crosstalk Mitigation with Double Microring Resonators and Data Encoding for Photonic NoC”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 26, iss. 1, pp. 168 – 181, Jan 2018.
K. Yao, Y. Ye, S. Pasricha, J. Xu, “Thermal-Sensitive Design and Power Optimization for a 3D Torus-Based Optical NoC,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov 2017.
I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct 2017.
S. V. R. Chittamuru, S. Desai, S. Pasricha, “SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast Enabled Channel Sharing for Multicore Architectures”, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 13, No. 4, pp. 58:1-58:27, Jun 2017.
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “Analyzing Voltage Bias and Temperature Induced Aging Effects in Photonic Interconnects for Manycore Computing,” ACM System Level Interconnect Prediction Workshop (SLIP), Jun 2017.
D. Dang, S. V. R. Chittamuru, R. N. Mahapatra, S. Pasricha, “Islands of Heaters: A Novel Thermal Management Framework for Photonic NoCs,” IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Jan 2017.
I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2016.
I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Aug 2016.
I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects,” ACM/IEEE System Level Interconnect Prediction Workshop (SLIP), Jun 2016. (Best Paper Award)
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs ,” IEEE/ACM Design Automation Conference (DAC), Jun. 2016.
S. Bahirat, S. Pasricha, “A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip Synthesis”, Electronics, Special Issue on Rapid System Design with Dedicated Architectures and Specific Software Tools, 5(2), 21, 2016.
S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures,” IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2016. (Best Paper Award Candidate)
S. V. R. Chittamuru, S. Pasricha, “SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip,” IEEE International Conference on VLSI Design (VLSI), Jan 2016.
S. V. R. Chittamuru, S. Pasricha, “Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures”, IEEE Design and Test (D&T), vol.32, no.3, pp.29-39, June 2015.
S. V. R. Chittamuru, S. Pasricha, “Improving Crosstalk Resilience with Wavelength Spacing in Photonic Crossbar-based Network-on-Chip Architectures,” IEEE MWSCAS 2015.
S. V. R. Chittamuru, S. Desai, S. Pasricha, “A Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures,” ACM GLSVLSI, May 2015. (Best Paper Award)
Y. Xu, S. Pasricha, “Silicon Nanophotonics for Future Multicore Architectures: Opportunities and Challenges”, IEEE Design and Test (D&T), Special Issue on Silicon Nanophotonics for Future Multicore Architectures, Sep/Oct, pp. 9-17, 2014.
S. Bahirat, S. Pasricha, “METEOR: Hybrid Photonic Ring-Mesh Network-on-Chip for Multicore Architectures”, ACM Transactions on Embedded Computing Systems (TECS), 13(3):116:1-116:33, Mar 2014.
S. Bahirat, S. Pasricha, “HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific Network-On-Chip Architectures”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2014.
S. Bahirat, S. Pasricha, “3D HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific 3D Network-On-Chip Architectures”, Workshop on Exploiting Silicon Photonics for Energy efficient Heterogeneous Parallel Architectures (SiPhotonics), Jan. 2014.
S. Bahirat, S. Pasricha, “A Particle Swarm Optimization Approach for Synthesizing Application-specific Hybrid Photonic Networks-on-Chip”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2012.
S. Pasricha, S. Bahirat, “OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs“, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2011
S. Bahirat, S. Pasricha, “UC-PHOTON: A Novel Hybrid Photonic Network-on-Chip for Multiple Use-Case Applications“, IEEE International Symposium on Quality Electronic Design (ISQED) Santa Clara, CA, Mar 2010 (Best Paper Award)
S. Bahirat, S. Pasricha, “Exploring Hybrid Photonic Networks-on-Chip for Emerging Chip Multiprocessors“, IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Grenoble, France, Oct 2009
S. Pasricha, N. Dutt, “ORB: An On-chip Optical Ring Bus Communication Architecture for Multi-Processor Systems-on-Chip“, IEEE Asia & South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, Jan 2008