Disclaimer: The following publications are covered by copyright. Permission to make digital/hard copy of all or part of the following papers, technical reports, and presentations for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission.
Books
| B1 | S. Pasricha, and N. Dutt. “On-Chip Communication Architectures”, Morgan Kauffman, ISBN 978-0-12-373892-9, Apr 2008 [link] |
Book Chapters
| BC2 | S. Pasricha, Y. Zou, “Hybrid Partially Adaptive Fault Tolerant Routing for 3D Networks-on-Chip”, to appear, Topics in Embedded Systems, edited by CRC Press, 2012 |
| BC1 | S. Pasricha, N. Dutt, “On-chip optical ring bus communication architecture for heterogeneous MPSoC”, To appear, “Integrated optical interconnect architectures and applications in embedded systems”, edited by Springer, 2011 |
Peer Reviewed Journal Articles
| J19 | Y. Zou, Y. Xiang, S. Pasricha, “Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors”, Accepted for publication, IEEE Embedded System Letters, 2012. |
| J18 | D. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Deadline and Energy Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment”, Accepted for publication, Journal of Supercomputing, 2012. |
| J17 | N. Kapadia, S. Pasricha, "A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands ", Accepted for publication, Integration, the VLSI Journal, 2011. |
| J16 | L. Bathen, Y. Ahn, S. Pasricha, N. Dutt, “MultiMaKe: Chip-Multiprocessor Driven Memory-aware Kernel Pipelining”, Accepted for publication, IEEE Transactions on Embedded Computing Systems (TECS), 2011. |
| J15 |
Y. Park,
S. Pasricha, F. Kurdahi, N. Dutt, "A
Multi-Granularity Power Modeling Methodology for Embedded
Processors"
,
IEEE Transactions on Very Large Scale Integration
Systems (TVLSI), Vol. 19, No. 4, pp. 668-681, Apr 2011
 |
| J14 |
Y. Zou, S. Pasricha, "NARCO: Neighbor Aware Turn Model Based
Fault Tolerant Routing for NoCs", IEEE Embedded System Letters,
Vol. 2, No. 3, Sep 2010.
|
| J13 |
S. Pasricha, F. Kurdahi, N. Dutt, "Evaluating
Carbon Nanotube Global Interconnects for Chip Multiprocessor
Applications",
IEEE
Transactions on Very Large Scale Integration Systems (TVLSI),
Vol. 18, No. 9, pp. 1376-1380, Sep 2010.
|
| J12 |
S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, "CAPPS:
A Framework for Power-Performance Trade-Offs in Bus Matrix
Based On-Chip Communication Architecture Synthesis",
IEEE Transactions on Very Large
Scale Integration Systems (TVLSI), Vol. 18, No. 2, pp.
209-221, Feb 2010.
|
| J11 |
G. Madl, S. Pasricha, N. Dutt, S. Abdelwahed,
"Cross-abstraction Functional Verification and Performance
Analysis of Chip Multiprocessor Designs",
IEEE Transactions on Industrial
Informatics (TII), Vol. 5, No. 3, Aug
2009
|
| J10 |
D. Cho, S.
Pasricha, I. Issenin, N. Dutt, Y. Paek , "Adaptive
Scratch Pad Memory Management for Dynamic Behavior of
Multimedia Applications",
IEEE
Transactions on Computer-Aided Design of Integrated Circuits
and Systems, (TCAD), Vol. 28, No. 4, pp.
554-567, Apr
2009
|
| J9 |
S.
Pasricha, Y. Park, F. Kurdahi, N. Dutt, "System-level PVT Variation Aware Power
Exploration of On-Chip Communication Architectures",
ACM Transactions on Design Automation of
Electronic Systems (TODAES), Vol. 14, No. 2, pp.
20:1-20:25, Mar 2009
|
| J8 |
S.
Pasricha, N. Dutt, "Trends in Emerging On-Chip Interconnect
Technologies",
IPSJ
Transactions on System LSI Design Methodology,
Vol. 1, Sep 2008
|
| J7 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Fast Exploration of
Bus-based Communication Architectures at the CCATB
Abstraction", IEEE Transactions on Embedded Computing
Systems (TECS),
Feb 2008
|
| J6 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "BMSYN: Bus Matrix
Communication Architecture Synthesis for MPSoC",
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, (TCAD), vol.26, no.8, pp.1454-1464,
Aug 2007
|
| J5 |
S.
Pasricha, N. Dutt, "A Framework for Co-synthesis of Memory
and Communication Architectures for MPSoC", IEEE
Transactions on Computer-Aided Design of Integrated Circuits
and Systems (TCAD),
Vol. 26, No. 3, pp. 408-420,
Mar 2007
|
| J4 | C. Shin, P. Grun, N. Romdhane, C. Lennard, G. Madl, S. Pasricha, N. Dutt, M. Noll, "Enabling Heterogeneous Cycle-Based and Event-Driven Simulation in a SPIRIT-Enabled Design Flow", Kluwer Journal on Design Automation of Embedded Systems (DAES), Feb 2007 [link] |
| J3 |
S.
Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, "FABSYN:
Floorplan-aware Bus Architecture Synthesis”,
IEEE
Transactions on Very Large Scale Integration Systems
(TVLSI), Vol 14, No. 3, pp 241-253,
Mar 2006
|
| J2 | S. Pasricha,
M. Luthra, S. Mohapatra, N. Dutt, N. Subramanian, "Dynamic
Backlight Adaptation for Low Power Handheld Devices", IEEE
Design and Test (IEEE D&T), Special Issue on Embedded
Systems for Real Time Embedded Systems,
Sep-Oct 2004
|
| J1 | S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, N. Subramanian, "Co-optimization of Streaming Multimedia QoS and Backlight Power Consumption for Mobile Handheld Devices", Special Issue Journal of Korean Multimedia Society (KSSM), Dec 2003 |
Peer Reviewed Conference and Workshop Papers
| C47 | A. M. Al-Qawasmeh, S. Pasricha, A. M. Maciejewski, and H. J. Siegel, “Thermal-Aware Performance Optimization in Power Constrained Heterogeneous Data Centers”, to appear, 21st International Heterogeneity in Computing Workshop, 2012. |
| C46 | B. Donohoo, C. Ohlsen, S. Pasricha, C. Anderson, “Exploiting Spatiotemporal and Device Contexts for Energy-Efficient Mobile Embedded Systems”, to appear, IEEE/ACM Design Automation Conference (DAC), Jul. 2012. |
| C45 | S. Bahirat, S. Pasricha, “A Particle Swarm Optimization Approach for Synthesizing Application-specific Hybrid Photonic Networks-on-Chip”, To appear, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2012. |
| C44 | N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands”, IEEE International Conference on VLSI Design (VLSID), Jan. 2012. |
| C43 | S. Pasricha, “A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip”, IEEE International Conference on VLSI Design (VLSID), Jan. 2012. |
| C42 | Y. Zou, Y. Xiang, S. Pasricha, “Analysis of On-chip Interconnection Network Interface Reliability in Multicore Systems”, IEEE International Conference on Computer Design (ICCD), Oct. 2011. |
| C41 | B. Donohoo, C. Ohlsen, S. Pasricha, “AURA: An Application and User Interaction Aware Middleware Framework for Energy Optimization in Mobile Devices”, IEEE International Conference on Computer Design (ICCD), Oct. 2011. |
| C40 | D. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Energy-Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment”, to appear, Fourth International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2), Sep 2011. |
| C39 | J. Apodaca, D. Young, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Stochastically Robust Static Resource Allocation for Energy Minimization with a Makespan Constraint in a Heterogeneous Computing Environment”, to appear, ACS/IEEE International Conference on Computer Systems and Applications (AICCSA 2011), Dec 2011. |
| C38 |
N. Kapadia, S. Pasricha, “VISION: A Framework for Voltage
Island Aware Synthesis of Interconnection Networks-on-Chip”,
IEEE Great Lakes Symposium on VLSI (GLSVLSI 2011),
Lausanne, Switzerland, May 2011.
|
| C37 |
S. Pasricha, Y. Zou, "A Low Overhead Fault Tolerant Routing
Scheme for 3D Networks-on-Chip",
IEEE International Symposium on Quality Electronic Design (ISQED
2011)
, Santa Clara, CA,
Mar 2011
|
| C36 |
S. Kwon, S. Pasricha, "POSEIDON: A Framework for
Application-Specific Network-on-Chip Synthesis for
Heterogeneous Chip Multiprocessors",
IEEE International Symposium on Quality Electronic Design (ISQED
2011), Santa Clara, CA,
Mar 2011
|
| C35 |
S. Pasricha, Y. Zou, "NS-FTR: A Fault Tolerant Routing
Scheme for Networks on Chip with Permanent and Runtime
Intermittent Faults", IEEE/ACM
Asia & South Pacific Design Automation Conference (ASPDAC),
Yokohama, Japan,
Jan 2011
|
| C34 |
S. Pasricha, S. Bahirat, "OPAL: A Multi-Layer Hybrid
Photonic NoC for 3D ICs", IEEE/ACM
Asia & South Pacific Design Automation Conference (ASPDAC),
Yokohama, Japan, Jan 2011
|
| C33 |
S. Pasricha, Y. Zou, D. Connors, H. J. Siegel, "OE+IOE: A
Novel Turn Model Based Fault Tolerant Routing Scheme for
Networks-on-Chip", Proc. IEEE/ACM
International Conference on
Hardware/Software Codesign and System Synthesis (CODES+ISSS),
Scottsdale, AZ, Oct
2010
|
| C32 | S. Pasricha, "Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors", 21st Annual Workshop on Interconnections within High Speed Digital Systems (HSD), Santa Fe, New Mexico, May 2010 (Invited) |
| C31 |
S. Bahirat, S. Pasricha, "UC-PHOTON: A Novel Hybrid Photonic
Network-on-Chip for Multiple Use-Case Applications",
IEEE International Symposium on Quality Electronic
Design (ISQED 2010) Santa Clara, CA,
Mar 2010 (Best
Paper Award)
|
| C30 |
L. A. D. Bathen, Y. Ahn, S. Pasricha,
N. Dutt, "A Methodology for Power-aware Pipelining via
High-Level Performance Model Evaluations", IEEE International Workshop on Microprocessor Test and
Verification
(MTV 2009), Austin, TX, Dec 2009
|
| C29 |
L. A. D. Bathen, Y. Ahn, N. Dutt,
S. Pasricha, "Inter-kernel Data Reuse and Pipelining on
Chip-Multiprocessors for Multimedia Applications",
IEEE Workshop on Embedded
Systems for Real-Time Multimedia (ESTIMedia 2009)
Grenoble, France, Oct 2009
|
| C28 |
S. Bahirat, S. Pasricha, "Exploring
Hybrid Photonic Networks-on-Chip for Emerging Chip
Multiprocessors",
IEEE/ACM International
Conference on Hardware/Software Codesign and System
Synthesis (CODES+ISSS 2009),
Grenoble, France,
Oct 2009
|
| C27 |
S. Pasricha, "Exploring
Serial Vertical Interconnects for 3D ICs", IEEE/ACM
Design Automation Conference (DAC 2009), San
Francisco, CA, Jul 2009
|
| C26 |
R. Kost, D. Connors, S. Pasricha, "Characterizing the Use of
Program Vulnerability Factors for Studying Transient Fault
Tolerance in Multi-core Architectures", Workshop
on Compiler and Architectural Techniques for Application
Reliability and Security (CATARS 2009)
Estoril, Portugal,
Jun 2009
|
| C25 |
A. Gupta, S. Pasricha, N. Dutt, F. Kurdahi,
K. Khouri, M. Abadir, "On-Chip Communication Architecture
Based Thermal Management for SoCs",
IEEE VLSI Design, Automation & Test (VLSI-DAT
2009), Hsinchu, Taiwan,
Apr 2009
|
| C24 |
S. Pasricha, N. Dutt, F. Kurdahi, "Dynamically
Reconfigurable On-Chip Communication Architectures for Multi
Use-Case Chip Multiprocessor Applications",
IEEE/ACM Asia & South
Pacific Design Automation Conference (ASPDAC 2009), Yokohama,
Japan,
Jan 2009
|
| C23 |
S.
Pasricha, F. Kurdahi, N. Dutt, "Exploring Carbon
Nanotube Bundle Global Interconnects for Chip Multiprocessor
Applications",
IEEE VLSI Design Conference (VLSID
2009),
New Delhi, India,
Jan
2009
|
| C22 | L. A. D. Bathen, N. Dutt,
S. Pasricha, "A Framework for Memory-aware
Multimedia Application Mapping on Chip-Multiprocessors",
IEEE Workshop on Embedded
Systems for Real-Time Multimedia (ESTIMedia 2008),
Atlanta, GA, Oct 2008
|
| C21 |
Y. Park,
S. Pasricha, F. Kurdahi, N. Dutt, " Methodology for
Multi-Granularity Embedded Processor Power Model Generation
for an ESL Design Flow”,
IEEE/ACM International Conference on
Hardware/Software Codesign and System Synthesis (CODES+ISSS
2008),
Atlanta, GA,
Oct 2008
|
| C20 |
S.
Pasricha, F. Kurdahi, N. Dutt, " System Level Performance
Analysis of Carbon Nanotube Global Interconnects for
Emerging Chip Multiprocessors”,
IEEE/ACM
International Symposium on Nanoscale Architectures, (NanoArch
2008), Anaheim, CA, Jun 2008
|
| C19 |
H.
Homayoun, S. Pasricha, M. Makhzan, A. Veidenbaum, "Dynamic
Register File Resizing to Improve Embedded Processor
Performance and Energy-delay Efficiency”,
IEEE/ACM Design and Automation Conference (DAC 2008),
Anaheim, CA,
Jun 2008
|
| C18 |
D. Cho, S.
Pasricha, I. Issenin, N. Dutt and Y. Paek, "Compiler Driven
Data Layout Optimization for Regular/Irregular Array Access
Patterns”,
ACM SIGPLAN/SIGBED Conference on
Languages, Compilers and Tools for Embedded Systems (LCTES
2008),
Tucson, AZ, Jun 2008
|
| C17 |
H.
Homayoun, S. Pasricha, M. Makhzan, A. Veidenbaum, "
Improving Performance and Reducing Energy-Delay with
Adaptive Resource Resizing for Out-of-Order Embedded
Processors ”, ACM SIGPLAN/SIGBED Conference on
Languages, Compilers and Tools for Embedded Systems (LCTES
2008), Tucson, AZ, Jun 2008
|
| C16 |
S.
Pasricha, Y. Park, S. Pasricha, Y. Park, F. Kurdahi, N.
Dutt, " Incorporating PVT Variations in System-level Power
Exploration of On-Chip Communication Architectures”,
IEEE VLSI Design Conference (VLSID
2008), Bangalore, India,
Jan 2008
|
| C15 |
S.
Pasricha, N. Dutt, "ORB: An On-chip Optical Ring Bus
Communication Architecture for Multi-Processor
Systems-on-Chip", IEEE Asia & South
Pacific Design Automation Conference (ASPDAC 2008),
Seoul, Korea,
Jan 2008
|
| C14 |
Y. Park,
S. Pasricha, F. Kurdahi, N. Dutt, "System Level Power
Estimation Methodology with H.264 Decoder Prediction IP Case
Study", IEEE
International Conference on Computer Design (ICCD 2007),
Great Lakes, CA,
Oct 2007
|
| C13 | S. Pasricha, N. Dutt, "On-chip Communication Architecture Synthesis for High Performance MPSoCs", SRC TechConnect, Nov 2007 |
| C12 |
S.
Pasricha, Y. Park, F. Kurdahi, N. Dutt, “System-Level
Power-Performance Trade-Offs in Bus Matrix Communication
Architecture Synthesis”, IEEE/ACM International Conference on
Hardware/Software Codesign and System Synthesis (CODES+ISSS
2006), Seoul, Korea,
Oct
2006
|
| C11 |
G. Madl,
S. Pasricha, Q. Zhu, L. Bathen, N. Dutt, "Formal Performance
Evaluation of AMBA-based System-on-Chip Designs", 6th
Annual ACM Conference on Embedded Software (EMSOFT 2006),
Seoul, Korea,
Oct 2006
|
| C10 |
S.
Pasricha, N. Dutt, "COSMECA: Application Specific
Co-Synthesis of Memory and Communication Architectures for
MPSoC", IEEE/ACM Design Automation and Test in Europe
Conference (DATE 2006), Munich, Germany,
Mar
2006
|
| C9 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Constraint-Driven Bus
Matrix Synthesis for MPSoC", IEEE/ACM Asia and South Pacific
Design Automation Conference (ASPDAC 2006), Yokohama,
Japan, Jan 2006
(Best Paper
Award)
|
| C8 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Using TLM for
Exploring Bus-based SoC Communication Architectures",
IEEE
International Conference on Application-specific Systems,
Architectures and Processors (ASAP 2005), Samos,
Greece,
Jul 2005
(invited paper)
|
| C7 |
S.
Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, "Floorplan-aware
Automated Synthesis of Bus-based Communication
Architectures",
IEEE/ACM Design and Automation Conference (DAC 2005),
Anaheim, CA,
Jun 2005
(Best
Paper Candidate)
|
| C6 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Automated
Throughput-driven Synthesis of Bus-based Communication
Architectures", Asia and South Pacific Design
Automation Conference (ASPDAC 2005), Shanghai, China,
Jan 2005
|
| C5 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Fast Exploration of
Bus-based On-chip Communication Architectures",
International Conference on Hardware/Software Codesign and
System Synthesis (CODES+ISSS 2004), Stockholm, Sweden,
Sep 2004
|
| C4 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Extending the
Transaction Level Modeling Approach for Fast Communication
Architecture Exploration", Design and Automation
Conference (DAC 2004), San Diego, CA,
Jun 2004
|
| C3 |
S.
Pasricha, S. Mohapatra, M. Luthra, N. Dutt, N. Subramanian,
"Reducing Backlight Power Consumption for Streaming Video
Applications on Mobile Handheld Devices", Embedded
Systems for Real-Time Multimedia (ESTIMedia 2003),
Newport Beach, CA,
Oct 2003
|
| C2 |
S.
Pasricha, A. Veidenbaum, "Improving Branch Prediction
Accuracy in Embedded Processors in the Presence of Context
Switches" International Conference on Computer Design
(ICCD 2003), San Jose, CA,
Oct 2003
|
| C1 |
S.
Pasricha, "Transaction Level Modeling of SoC with
SystemC 2.0" Synopsys User Group Conference (SNUG
2002), Bangalore,
May 2002
|
Conference Tutorials
| TU4 | S. Pasricha, N. Dutt, L. Benini, “On-Chip Communication Architectures: Buses, Networks-on-Chip, and Beyond ”, Full day tutorial at 41st IEEE/ACM International Symposium on Microarchitecture (MICRO 2008), Lake Como, Italy, Nov 2008 |
| TU3 | S. Pasricha, K. Lahiri, and N. Dutt, “Modeling, Analysis and Design of Bus-based SOC Communication Architectures”, Half day tutorial at IEEE Design Automation and Test in Europe, (DATE 2007), Nice, France, Apr 2007 |
| TU2 | S. Pasricha, K. Banerjee, L. Benini, K. Lahiri and N. Dutt, “SoC Communication Architectures: Technology, Current Practice, Research and Trends”, Full day tutorial at IEEE VLSI Design Conference (VLSID 2007), Bangalore, India, Jan 2007 |
| TU1 | S. Pasricha, N. Dutt, "SoC Communication Architectures: Current Practice, Research and Trends", Half day tutorial at the Asia and South Pacific Design Automation Conference (ASPDAC 2006), Yokohama, Japan, Jan 2006 |
Workshop and Seminar Presentations
| PR3 | S. Pasricha, "Networks on Chips and Beyond", Barney's Monday Afternoon Club (BMAC) Seminar, CS Dept., CSU Nov 2009 |
| PR2 | S. Bahirat, S. Pasricha, "Design and Exploration of the PHOTON Hybrid Nanophotonic-electric On-chip Communication Architecture", IEEE CANDE Workshop, Oct 2009 |
| PR1 | S. Pasricha, "Customizing Memories for MPSoCs", Workshop on Compiler-Assisted System-On-Chip Assembly (CASA) Oct 2009 |
Posters
| P6 | N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip”, IEEE Computer-Aided Network DEsign CANDE Workshop, Oct. 2011. |
| P5 | D. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Energy-Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment”, FRCRC First Annual Front Range High Performance Computing Symposium, Oct. 2011. (Winner of Best Poster Award) |
| P4 | S. Bahirat, S. Pasricha, "Design and Exploration of the PHOTON Hybrid Nanophotonic-electric On-chip Communication Architecture", IEEE CANDE Workshop, Oct 2009. |
| P3 | S. Pasricha, “COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor System-on-Chips”, ICS Seminar, May 2007 |
| P2 | S. Pasricha, N. Dutt, M. Ben-Romdhane, "Fast Exploration of Bus-based Communication Architectures", CECS ISLPD Open House 2004, Irvine, CA, Aug 2004 |
| P1 | S. Pasricha et al, "Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices", Southern California Embedded Systems Symposium (SCESS) 2003, Irvine, CA, Sep 2003 (Winner of 2nd Place SCESS Best Poster Award) |
Thesis
| TH1 | S. Pasricha, “COMMSYN:
On-Chip Communication Architecture Synthesis for
Multi-Processor Systems-on-Chip ”, Ph.D. Thesis,
University of California, Irvine,
Jun 2008
|
(Old) Technical Reports
| TR9 |
S.
Pasricha, Y. Park, F. Kurdahi and N. Dutt,
"Power-Performance Trade-Offs for Bus Matrix Communication
Architectures",
CECS Technical Report 06-12,
Nov 2006
|
| TR8 |
S.
Pasricha, N. Dutt, "A Framework for Memory and Communication
Architecture Co-synthesis in MPSoCs,"
CECS
Technical Report 06-03, Feb 2006 |
| TR7 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Bus Matrix
Communication Architecture Synthesis,"
CECS
Technical Report 05-13, Oct 2005
|
| TR6 |
S.
Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, "Floorplan-aware
Bus Architecture Synthesis," CECS Technical Report
04-27,
Oct 2004
|
| TR5 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "Automated Synthesis of
Bus Architectures for Systems with Throughput Constraints",
CECS Technical Report 04-20,
Aug 2004
|
| TR4 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane,
"Rapid Exploration of Bus-based Communication Architectures
at the CCATB Abstraction", CECS Technical
Report 04-11,
May 2004
|
| TR3 |
S.
Pasricha, N. Dutt, M. Ben-Romdhane, "High Level Design
Space Exploration of Shared Bus Communication
Architectures", CECS Technical Report 04-06,
Mar 2004
|
| TR2 |
S.
Pasricha, A. Veidenbaum, "Novel Techniques to Improve Branch
Prediction Accuracy for Embedded Processors in the Presence
of Context Switches", CECS Technical Report 03-24,
Aug 2003
|
| TR1 |
S.
Pasricha, P. Mishra, P. Biswas, A. Shrivastava, A. Mandal,
N. Dutt, A. Nicolau, "A Framework for GUI-driven Design
Space Exploration of a MIPS4K-like processor", CECS
Technical Report 03-17,
Apr 2003
|
User Manuals
| U1 |
P. Biswas,
S. Pasricha, P. Mishra, A. Shrivastava, A. Nicolau, N. Dutt
"EXPRESSION User Manual Version 1.0"
|