Research

My primary research goals are focused on the development of high performance computing systems and interconnects employing emerging technologies while emphasizing on energy-efficiency and robustness. Some topics of interest are:

  • Silicon Photonics 
  • High Performance Computing
  • Heterogeneous Embedded and Computing Systems
  • Multiprocessor Systems-on-Chip (MPSoCs)
  • Interconnection Networks
  • Systems Modeling and Simulation
  • Design for Reliability and Energy Efficiency
  • Advanced Computer Architectures
  • Computer Vision

This page reviews some of my research activities. Link to all relevant publications can be found here.

Enhancing Performance and Reliability in Silicon Photonic Integrated Circuits

Microresonators (MRs), which are widely employed in silicon photonic integrated circuits (PICs), are considerably sensitive to fabrication process variations (PV). Particularly, such variations deviate the resonant wavelength of MRs, resulting in performance and reliability degradation in PICs utilizing MRs for modulating, filtering, and switching optical signals. Several methods have been proposed to compensate for PV, and specifically to restore the resonant wavelength of MRs, including those based on applying high-energy particles (e.g., UV light), but at a cost of degrading MRs quality factor, and also trimming techniques (e.g., thermal tuning), which are power hungry and often have a limited correction range. In this project, we demonstrate an efficient device-level design method, called DeEPeR, to improve MRs reliability in PICs under fabrication process variations. Considering different range of variations, DeEPeR explores the design space of MRs to study how employing different design parameters in such components impacts the resonant wavelength shift, and hence MRs performance and reliability. Also, our study includes the design and fabrication of several MRs using DeEPeR for experimental validation. Indicating the impact of DeEPeR in PICs, we apply our method to a case study of a wavelength division multiplexed (WDM) optical filter, in which we show how the optical signal-to-noise ratio (OSNR) considerably improves (5.2 dB on average) when using DeEPeR. The OSNR determines the received optical signal quality and the bit error rate (BER) in a system, hence denoting the performance and reliability.

Figure: Measured through and drop port responses of the fabricated MRs without and with using DeEPeR (20 passive MRs in total with same radii).

Figure: The optical SNR (box-plots) associated with different optical wavelengths on the drop port of a passive optical filter (with four MRs) under 100 different process variation maps: (a) Without using DeEPeR and (b) When DeEPeR is applied.


Design Space Exploration for Fundamental Devices in Silicon Photonic Interconnects

The design of fundamental photonic devices in silicon photonic interconnects involves considering multiple constraints and objectives, which are very often competing. For example, considering microresonators (MRs) in silicon photonic interconnects, on one hand, the radius must be large enough to prevent undesired high bending losses (i.e. radiation and scattering), especially when used in a drop configuration, but must also remain small enough to avoid multiple resonances in the optical bandwidth of interest. Also, a larger radius results in a strong coupling of the ring to the waveguides (increasing 3dB bandwidth) while at the same time it results in a smaller optical loss of the ring (decreasing 3dB bandwidth). Under such multiple constraints (and several more), the selection of a ring with right parameters is not a straightforward process. Particularly, in some cases, no realistic MR matching all the requirements exists. In this project we propose a method to enable system designers to explore the design space of MRs, identifying whether MRs matching different requirements can be fabricated and how they should be designed. The proposed method includes two compact models and has a high computational efficiency. Firstly, we study the optical mode coupling in MRs under different ring geometrical parameters. Secondly, we study the loss in MRs based on the ring diameter. Our results indicate that the design space for add-drop filters in a wavelength division multiplexed link is currently limited to 5 to 10 µm in radius and gap sizes ranging from 120 nm to 210 nm. The good agreement between the results from the proposed compact model for coupling and the numerical FDTD and experimental measurements indicate the application of our approach in realizing fast and efficient design space exploration of MRRs in silicon photonic interconnects.

Figure: Characterization of design space for MR Add-drop filters based on strip waveguides and the baseline loss model. (a) Contours of attenuation at the resonance. The white area corresponds to less than 1 dB attenuation. (b) Contours of attenuation at half FSR. White area corresponds to attenuation better than 30 dB. (c) Contours of 3 dB optical bandwidth. White area corresponds to a bandwidth greater than 10 GHz and less than 50 GHz. (d) Overall design space of add-drop ring filters.


Design Space Exploration in Embedded Systems 

Designing complex embedded systems requires simultaneous optimization of multiple system performance metrics that can be addressed by applying Pareto-based multiobjective optimization techniques. At the end of this type of optimization process, designers always face Pareto fronts (PFs) including a large number of near-optimal solutions from which selecting the most proper system implementation is potentially infeasible. In this project, for the first time, we present HypAp, a hypervolume-based automated approach to systematically help designers efficiently choose their preferred solutions after the optimization process. HypAp is a two-stage approach relying on clustering Pareto optimal solutions and then finding a subset of solutions that maximizes the hypervolume by using a genetic algorithm. The performance of HypAp is evaluated through applying HypAp to the PF by the case study of mapping applications on network-on-chip (NoC) based heterogeneous MPSoC. We define several quality indicators, including hypervolume, nonuniformity, and outer-diameter, to evaluate the similarity and effectiveness of the reduced PF (RPF) compared to the PF. 

Figure: Apply HypAp to the PF of a network-on-chip (NoC) mapping optimization problem: (a) PF obtained by mapping the generated task graphs on the NoC architecture along with its (b) 2-D illustration including the clusters and RPF.


Studying Fabrication Process Variation in Silicon Photonic Integrated Circuits

Silicon photonic interconnect (SPI) is an attractive alternative for the power-hungry and low-bandwidth metallic interconnect in multiprocessor systems-on-chip (MPSoCs). When employing SPIs for wavelength-division multiplexing (WDM)-based applications, it is essential to precisely align the central wavelengths of different photonic devices (e.g., photonic switches) to achieve a reliable communication. However, SPIs are sensitive to fabrication non-uniformity (a.k.a. fabrication process variation), which results in wavelength mismatches between devices, and hence performance degradation in SPIs. This project presents a computationally efficient and accurate bottom-up approach to study the impact of fabrication process variations on passive silicon photonic devices and interconnects. We model the impact of process variations at the component level, device level, and finally at the system level. Numerical simulations are performed not only to evaluate the accuracy of our method, but also to demonstrate its high-computational efficiency. Furthermore, our study includes the design, fabrication, and analysis of several identical microresonators to demonstrate process variations in silicon photonics fabrication. The efficiency of our proposed method enables its application to large-scale passive SPIs in MPSoCs, where employing time-consuming numerical simulations is not feasible.

 
Figure (left-hand side): An overview of the proposed bottom-up approach to study the impact of fabrication process variations on MPSoCs integrating silicon photonic interconnects.
Figure (right-hand side): Resonance wavelength shift contours versus the physical position of the MRs (x and y) fabricated (EBeam) on a 2 mm x 4mm chip and when the nominal designed resonance is at 1550 nm. 

Low-Latency Centralized Controller for Optical Integrated Networks 

Optical interconnection network (OIN) is a promising alternative to overcome the restrictions that electrical networks-on-chip (eNoCs) will face in the next generation of multiprocessor integrated systems due to electrical interconnects physical limitations. OINs present a higher bandwidth and lower power consumption but their full capabilities are curbed by high latency controllers. Control techniques, such as circuit switching, impose a high latency to perform the correct network routing and a better solution must be found in order to fully utilize OINs. In this project, we have designed and modeled a low-latency centralized controller (LUCC) for optical interconnects. For validation purposes, we modeled different Mach-Zehnder interferometer (MZI)-based optical interconnects that employ the proposed LUCC. We obtain a response time of only one clock cycle when using LUCC even when conflicts are found. To demonstrate the feasibility of LUCC, we realized a complete setup where both system and physical layers are co-designed towards an efficient demonstration of photonic integration potential. The interface of the two layers is done using available ports of the FPGA, such as General Purpose I/O (GPIO) and SMA ports. For the proposed setup, a 10 MHz operation frequency is used due to bandwidth limitation of GPIO ports. The system layer is entirely deployed using Altera’s FPGAs technology executing the following tasks: 1) the system controller, namely our novel Look-up Table Centralized Controller (LUCC) algorithm, 2) data pattern generators, 3) fast transceivers units serializing and deserializing the payload data, and 4) an error detector unit allocating temporary memories to store the generated payload and the received payload data for error detection purpose.

Figure: An overview of the proposed low-latency controller (LUCC) and its interaction with a PIC.

Figure: (a) MZI-based prototyped photonic switch; (b) overview of the FPGA-based LUCC co-designed with the MZI-based multistage photonic switch; and, (c) 4×4 MZI-based photonic switch readings.


Formal Study of Signal-to-noise Ratio (SNR) in Optical Interconnection Networks 

Photonic devices, which are widely used in constructing optical routers and optical interconnects, intrinsically suffer from crosstalk noise and power loss, but the crosstalk noise and power loss from photonic devices are very small and, hence, have been ignored. However, this raises the question of whether in large scale networks consisting of thousands of optical devices, where the crosstalk noise accumulates and, simultaneously, the power loss rises on an optical signal, the crosstalk noise and power loss from photonic devices can be still neglected. This project answered this question in a variety of optical interconnect architectures. To the best of my knowledge, for the first time, this project studied and modeled the worst-case as well as the average crosstalk noise and SNR in arbitrary mesh-based, folded-torus-based, fat-tree-based, and ring-based optical interconnection networks at the system level. We demonstrate that crosstalk is a critical issue in optical interconnection networks which severely limits the scalability of such interconnects and also degrades their performance.

Figure: Crosstalk in basic optical elements and switching elements in passive optical interconnects: (a) Waveguide crossing, (b) photonic switching element in ON and OFF states, (c) Optical terminator, and (d) crossing switching element in ON and OFF states.

Crosstalk and Loss Analysis Platform (CLAP) Simulator

To facilitate the crosstalk noise and SNR analyses in arbitrary optical interconnection networks, we integrated our proposed formal analytical models at the basic photonic device and optical router levels into a newly developed analysis platform, called CLAP. CLAP has two major functions. Firstly, it is capable of analyzing the signal power, crosstalk noise power, and SNR at the destination of an optical link in an arbitrary optical interconnect, while also providing the worst-case results at that destination. Secondly, the optical router function helps analyze the signal power, crosstalk noise power, and SNR in an arbitrary optical router structure. This analyzer is implemented in C++ and is publicly released. CLAP has a complete library of the photonic devices, including waveguides, MRs, parallel switching elements, crossing switching elements, and optical terminators, required to construct optical interconnects and optical routers. It is the first crosstalk and loss analysis platform proposed for optical interconnects that has been widely used by many research groups worldwide.

Figure: CLAP’s internal structure.

An Innovation Intermittent Routing Algorithm for Networks-On-Chip (NoCs)

Network-on-Chip (NoC) is a novel communication infrastructure for multiprocessor systems-on-chip (MPSoCs). In such networks, the routing algorithm plays an important role as it determines the efficiency of the communication in the network. XY (a.k.a. dimension ordered routing algorithm) is a well-known routing technique that has low latency and implementation cost. Inspiring by XY, we propose an intermittent XY-YX routing algorithm, called IXY. IXY interchangeably routes packets using XY and YX routing techniques. The simulation results demonstrate that IXY has a better energy efficiency and considerably lower latency compared to other routing algorithms in NoCs. (Undergraduate research).

Figure: Comparison of the average delay in a 4×4 mesh-based NoC using different routing techniques, including IXY (Intermittent XY).