My primary research goals are focused on design methodologies and development of advanced embedded and computing systems employing emerging technologies while emphasizing on energy-efficiency and robustness for emerging applications. Some topics of interest are:

  • Heterogenous Embedded and Computing Systems
  • Multiprocessor Systems-on-Chip (MPSoCs)
  • Silicon Photonics
  • Interconnect
  • System Modeling and Simulation
  • Big Data Systems
  • Design for Reliability and Energy Efficiency
  • Computer Architecture

This page reviews some of my research activities. Link to all relevant publications can be found here.

Fabrication Process Variation in Chip-Scale Silicon Photonic Integrated Circuits

Silicon photonic interconnect (SPI) is an attractive alternative for the power-hungry and low-bandwidth metallic interconnect in multiprocessor systems-on-chip (MPSoCs). When employing SPIs for wavelength-division multiplexing (WDM)-based applications, it is essential to precisely align the central wavelengths of different photonic devices (e.g., photonic switches) to achieve a reliable communication. However, SPIs are sensitive to fabrication non-uniformity (a.k.a. fabrication process variation), which results in wavelength mismatches between devices, and hence performance degradation in SPIs. This project presents a computationally efficient and accurate bottom-up approach to study the impact of fabrication process variations on passive silicon photonic devices and interconnects. We first model the impact of process variations at the component level (i.e. strip waveguides), then at the device level (i.e. add-drop filters and photonic switches), and finally at the system level (i.e. passive WDM-based silicon photonic interconnects). Numerical simulations are performed not only to evaluate the accuracy of our method, but also to demonstrate its high-computational efficiency. Furthermore, our study includes the design, fabrication, and analysis of several identical microresonators to demonstrate process variations in silicon photonics fabrication. The efficiency of our proposed method enables its application to large-scale passive SPIs in MPSoCs, where employing time-consuming numerical simulations is not feasible.Overview

Figure: An overview of the proposed bottom-up approach to study the impact of fabrication process variations on MPSoCs integrating silicon photonic interconnects.
Figure: Resonance wavelength shift contours versus the physical position of the MRs (x and y) fabricated on a 2 mm x 4mm chip and when the nominal designed resonance is at 1550 nm. 

Low-Latency Centralized Controller for Optical Integrated Networks 

Optical integrated network (OIN) is a promising alternative to overcome the restrictions that electrical networks-on-chip (eNoCs) will face in the next generation of multiprocessor integrated systems due to electrical interconnects physical limitations. OINs present a higher bandwidth and lower power consumption but their full capabilities are curbed by high latency controllers. Control techniques, such as circuit switching, impose a high latency to perform the correct network routing and a better solution must be found in order to fully utilize OINs. In this project, we have designed and modeled a low-latency centralized controller (LUCC). For validation purposes, we modeled different Mach-Zehnder interferometer (MZI)-based optical interconnects that employ the proposed LUCC. We obtain a response time of only one clock cycle when using the LUCC, even when conflicts are found. In order to demonstrate the feasibility of LUCC, we realized a complete setup where both system and physical layers are co-designed towards an efficient demonstration of photonic integration potential. The interface of the two layers is done using available ports of the FPGA, such as General Purpose I/O (GPIO) and SMA ports. For the proposed setup, a 10 MHz operation frequency is used due to bandwidth limitation of GPIO ports. The system layer is entirely deployed using Altera’s FPGAs technology executing the following tasks: 1) the system controller, namely our novel Look-up Table Centralized Controller (LUCC) algorithm, 2) data pattern generators, 3) fast transceivers units serializing and deserializing the payload data, and 4) an error detector unit allocating temporary memories to store the generated payload and the received payload data for error detection purpose.

Figure: An overview of the proposed low-latency controller (LUCC).

Formal Study of Signal-to-noise Ratio (SNR) in Optical Networks-on-Chip (ONoCs) in MPSoCs 

Photonic devices, which are widely used in constructing optical routers and optical NoCs, intrinsically suffer from crosstalk noise and power loss, but the crosstalk noise and power loss from photonic devices are very small and, hence, have been ignored. However, this raises the question of whether in large scale ONoCs, where the crosstalk noise accumulates and, simultaneously, the power loss rises on an optical signal, the crosstalk noise and power loss from photonic devices can be still neglected. This project answered this question in a variety of ONoC architectures. To the best of my knowledge, for the first time, this project studied and modeled the worst-case as well as the average crosstalk noise and SNR in arbitrary mesh-based, folded-torus-based, fat-tree-based, and ring-based ONoCs at the system level. We demonstrated that crosstalk is a critical issue in optical interconnection networks which severely limits the scalability of such interconnects and also degrades their performance.

Crosstalk noise
Figure: Crosstalk in basic optical elements and switching elements in passive optical interconnects: (a) Waveguide crossing, (b) photonic switching element in ON and OFF states, (c) Optical terminator, and (d) crossing switching element in ON and OFF states.

Crosstalk and Loss Analysis Platform (CLAP) Simulator

To facilitate the crosstalk noise and SNR analyses in arbitrary ONoCs, we integrated our proposed formal analytical models at the basic photonic device and optical router levels into a newly developed analysis platform, called CLAP. CLAP has two major functions. Firstly, it is capable of analyzing the signal power, crosstalk noise power, and SNR at the destination of an optical link in an arbitrary ONoC, while also providing the worst-case results at that destination. Secondly, the optical router function helps analyze the signal power, crosstalk noise power, and SNR in an arbitrary optical router structure. This analyzer is implemented in C++ and is publicly released. CLAP has a complete library of the photonic devices, including waveguides, MRs, parallel switching elements, crossing switching elements, and optical terminators, required to construct ONoCs and optical routers. It is the first crosstalk and loss analysis platform proposed for optical NoCs that has been widely used by many research groups worldwide.

Figure: CLAP’s internal structure.

An Innovation Intermittent Routing Algorithm for Networks-On-Chip (NoCs)

Network-on-Chip (NoC) is a novel communication infrastructure for multiprocessor systems-on-chip (MPSoCs). In such networks, the routing algorithm plays an important role as it determines the efficiency of the communication in the network. XY (a.k.a. dimension ordered routing algorithm) is a well-known routing technique that has low latency and implementation cost. Inspiring by XY, we proposed an intermittent XY-YX routing algorithm, called IXY. IXY interchangeably routes packets using XY and YX routing techniques. The simulation results demonstrate that IXY has a better energy efficiency and considerably lower latency compared to other routing algorithms in NoCs. (Undergraduate research).

IXY Latency
Figure: Comparison of the average delay in a 4×4 mesh-based NoC using different routing techniques, including IXY (Intermittent XY).