I have moved to the University of Kentucky. Please visit me there.

US Patents

P1 U.S. provisional patent application serial no. 61/970,155, entitled “Low Cost Chemical and Biochemical Sensor”, filed on 3/25/14. Inventors: I. Thakkar, K.L. Lear, K.F. Reardon

Book Chapters

BC1 S. Pasricha, S. V. R. Chittamuru, I. Thakkar, “'Enhancing Process Variation Resilience in Photonic NoC Architectures'”, to appear, Optical Interconnects for Computer Systems, River Publishers, 2016.

Peer-Reviewed Journal Articles

J1 Ishan Thakkar, Kevin L Lear, Jonathan Vickers, Brian Heinze and Kenneth Reardon, "A plastic total internal reflection photoluminescence device for enzymatic biosensing", Lab Chip, 2013, 13, 4775.
J2 Ishan Thakkar, Sudeep Pasricha, "3D-WiRED: A Novel Wide-I/O DRAM With Energy-Efficient 3D Bank Organization", IEEE Design and Test (D&T), 2015..
J3 Ishan Thakkar, Sudeep Pasricha, "3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead", IEEE Transactions on Multi-Scale Computing Systems (TMSCS), 2015..
J4 S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “HYDRA: Heterodyne Crosstalk Mitigation with Double Microring Resonators and Data Encoding for Photonic NoC”, to appear, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017.

Peer-Reviewed Conference Publications

C1 I. Thakkar, S. Pasricha, "3D-Wiz: A Novel High Bandwidth, Optically Interfaced 3D DRAM Architecture with Reduced Random Access Time," IEEE International Conference on Computer Design (ICCD), Oct 2014..
C2 S. Pasricha, I. Thakkar, "Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces," Memory Architecture and Organization Workshop (MeAOW), Oct 2014 (Invited)..
C3 I. Thakkar, S. Pasricha, "A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses," IEEE International Conference on Computer Design (ICCD), Oct 2015..
C4 I. Thakkar, S. Pasricha, "Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures," IEEE International Conference on VLSI Design (VLSI), Jan 2016.. [slides]
C5 SVR Chittamuru, I. Thakkar, S. Pasricha, "Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures," IEEE International Symposium on Quality Electronic Design (ISQED), Mar 2016. (Best Paper Award Candidate)
C6 SVR Chittamuru, I. Thakkar, S. Pasricha, "PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs," IEEE/ACM Design Automation Conference (DAC), June 2016..
C7 I. Thakkar, SVR Chittamuru, S. Pasricha, "Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers," IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Aug 2016..
C8 I. Thakkar, SVR Chittamuru, S. Pasricha, "A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects," ACM/IEEE System Level Interconnect Prediction Workshop (SLIP'16), June 2016. (Best Paper Award)
C9 I. Thakkar, SVR Chittamuru, S. Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling", ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2016.
C10 I. Thakkar, S. Pasricha, "DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency", IEEE International Conference on VLSI Design (VLSID), Jan 2017.
C11 SVR Chittamuru, I. Thakkar, S. Pasricha, "Analyzing Voltage Bias and Temperature Induced Aging Effects in Photonic Interconnects for Manycore Computing", ACM/IEEE System Level Interconnect Prediction Workshop (SLIP'17), June 2017.
C12 I. Thakkar, "Design and Optimization of Emerging Network-Memory Subsystems for Future Manycore Architectures", PhD Forum @ the 54th Design Automation Conference (DAC), June 2017.
C13 I. Thakkar, SVR Chittamuru, S. Pasricha, “Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), to appear in Oct 2017

More detailed publication list can be found in his CV.