ECE Seminar Series

ISTeC Distinguished Lecture in conjunction with the Computer Science and Electrical and Computer Engineering Department and Seminar Series

Title: Power-Efficient and Reliable Multicore Architectures
Speaker: Ahmed Louri
Affiliation: University of Arizona
Day: Monday, April 6, 2015
Time: 11:00 am - 12:00 pm
Location: Morgan Library Event Hall

Abstract: Today's microprocessor designers have been increasing the number of cores per die as a power-efficient approach to performance improvement, leading to the Chip Multiprocessors (CMPs) or the multicore era. Both industrial and academic roadmaps project that tera-operations per second CMPs will be needed within a decade to satisfy the nation's needs for high-performance computing. The proliferation of multiple cores on the same die heralded the advent of communication-centric designs, rather than computation-centric systems. The on-chip interconnect fabric connecting various modules, namely the processing cores, cache banks, memory units, and I/O devices, has become extremely important. Multicore designs have adopted a flexible and scalable packet-switched architecture called Network-on-Chip (NoC) architecture. Prof. Louri will present several research challenges facing multicore architectures and NoC design (e.g., power dissipation and reliability), and some of his group's ongoing efforts to address them. The talk will conclude with future research directions.

Bio: Ahmed Louri received the M.S. and Ph.D. degrees in Computer Engineering from the University of Southern California, Los Angeles, in 1984 and 1988, respectively. He joined the University of Arizona in 1988, where he is currently a Professor of Electrical and Computer Engineering and the Director of the High Performance Computing Architectures and Technologies Laboratory. From 2010 to 2013, he served as a Program Director in the Directorate for Computer and Information Science and Engineering (CISE) of the National Science Foundation with an annual research portfolio of $800 million. He managed the core computer architecture program and was on the management team of several cross-cutting programs including Cyber-Physical Systems (CPS), Expeditions in Computing (EIC), Computing Research Infrastructure (CRI), Trustworthy Computing (SaTC), and Failure-Resistant Systems (FRS). His primary research interests include computer architecture, parallel and distributed computing, interconnection networks, optical interconnects for parallel computing systems, reconfigurable computing systems, scalable and power-efficient architectures, fault-tolerant multiprocessors, Network-on-Chip for multi-core architectures, cognitive architectures, emerging interconnect technologies for multicores, embedded and SoC systems. He has published more than 125 journal articles and conference papers in these areas, and holds several US patents. He is a Fellow of IEEE.