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ECE Seminar Series




Title: Machine Learning-Inspired Manycore Chip Design: Interconnect architecture to power management
Speaker: Ryan Kim
Affiliation: School of ECE, Carnegie Mellon University
Day: Monday, February 26, 2018
Time: 11:00 am - 12:00 pm
Location: LSC 312

Abstract: Over the years, advances in silicon fabrication techniques have made it possible to steadily increase the number of processing cores on a single chip. Today, these manycore chips provide the compute power and form factor to enable the next generation of high-performance computing systems necessary for various applications, starting from autonomous vehicles to smartphones to fog/cloud computing. However, with such a high degree of integration, we need to explore suitable design optimization and power management techniques. In this seminar I will discuss several challenges and solutions for designing high-performance and energy-efficient manycore chips. In particular, I will focus on how recent advances in machine learning can be utilized to create effective design optimization mechanisms suitable for manycore-based single-chip computing systems. We will also discuss how these manycore chips can be enablers for emerging big-data applications. We will conclude this seminar by discussing our current work on how machine learning is able to assist in designing 3D heterogeneous systems for deep learning and how machine learning could assist in other possible future design challenges of manycore systems.

Bio: Ryan Kim is a postdoctoral fellow in the Department of Electrical and Computer Engineering at Carnegie Mellon University. He previously obtained his B.S. and Ph.D. in EECS from Washington State University in 2011 and 2016, respectively. His research interests include machine learning assisted hardware run-time control and design-time optimization, scalable power management, on-chip communication, and application-specific optimization, all within the context of manycore systems.