Graduate Exam Abstract
Ishan Thakkar
Ph.D. Final
May 10, 2018, 3:00 pm - 5:00 pm
LSC 226
DESIGN AND OPTIMIZATION OF EMERGING INTERCONNECTION AND MEMORY SUBSYSTEMS FOR FUTURE MANYCORE ARCHITECTURES
Abstract: With ever-increasing core count and
growing performance demand of
modern data-centric applications (e.g.,
big data and internet-of-things (IoT)
applications), energy-efficient and low-
latency memory accesses and data
communications (on and off the chip)
are becoming essential for emerging
manycore computing systems. But
unfortunately, due to their poor
scalability, the state-of-the-art electrical
interconnects and DRAM based main
memories are projected to exacerbate
the latency and energy costs of
memory accesses and data
communications. Recent advances in
silicon photonics, 3D stacking, and
non-volatile memory technologies
have enabled the use of cutting-edge
interconnection and memory
subsystems, such as photonic
interconnects, 3D-stacked DRAM, and
phase change memory. These
innovations have the potential to
enhance the performance and energy-
efficiency of future manycore systems.
However, despite the benefits in
performance and energy-efficiency,
these emerging interconnection and
memory subsystems still face many
technology-specific challenges along
with process, environment, and
workload variabilities, which negatively
impact their reliability overheads and
implementation feasibility. For
instance, with recent advances in
silicon photonics, photonic networks-
on-chip (PNoCs) and core-to-memory
photonic interfaces have emerged as
scalable communication fabrics to
enable high-bandwidth, energy-
efficient, and low-latency data
communications in emerging
manycore systems. However, these
interconnection subsystems still face
many challenges due to thermal and
process variations, crosstalk noise,
aging, data-snooping Hardware
Trojans (HTs), and high overheads of
laser power generation, coupling, and
distribution, all of which negatively
impact reliability, security, and energy-
efficiency. Along the same lines, with
the advent of through-silicon via (TSV)
technology, 3D-stacked DRAM
architectures have emerged as small-
footprint main memory solutions with
relatively low per-access latency and
energy costs. However, the full
potential of the 3D-stacked DRAM
technology remains untapped due to
thermal- and scaling-induced data
instability, high leakage, and high
refresh rate problems along with other
challenges related to 3D floorplanning
and power integrity. Recent advances
have also enabled Phase Change
Memory (PCM) as a leading
technology that can alleviate the
leakage and scalability shortcomings
of DRAM. But asymmetric write
latency and low endurance of PCM are
major challenges for its widespread
adoption as main memory in future
manycore systems.
My research has contributed several
solutions that overcome multitude of
these challenges and improve the
performance, energy-efficiency,
security, and reliability of manycore
systems integrating photonic
interconnects and emerging memory
(3D-stacked DRAM and phase change
memory) subsystems. The main
contribution of my thesis is a
framework for the design and
optimization of emerging
interconnection and memory
subsystems for future manycore
computing systems. The proposed
framework synergistically integrates
layer-specific enhancements towards
the design and optimization of
emerging main memory, PNoC, and
inter-chip photonic interface
subsystems. In addition to subsystem-
specific enhancements, we also
combine enhancements across
subsystems to more aggressively
improve the performance, energy-
efficiency, and reliability for future
manycore architectures.
Adviser: Dr. Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Dr. Wim Bohm
Member 3: Dr. Anura Jayasumana
Addional Members: Dr. Kevin Lear
Publications:
I. Thakkar, K. L. Lear, J. Vickers, B. Heinze and K. Reardon, "A plastic total internal reflection photoluminescence device for enzymatic biosensing," Lab Chip, vol. 13, no. 34, pp. 4775-4783, Dec 2013.
I. Thakkar, S. Pasricha, “3D-WiRED: A Novel WIDE I/O DRAM with Energy-Efficient 3-D Bank Organization,†IEEE Design & Test, vol. 32, no. 4, pp. 71-80, 2015.
I. Thakkar, S. Pasricha, “3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead,†IEEE Transactions on Multi-Scale Computing Systems (TMSCS), vol. 1, no. 3, pp. 168-184, Sept 2015. (Best Paper Candidate)
I. Thakkar, S.V.R. Chittamuru, S. Pasricha, “HYDRA: Heterodyne Crosstalk Mitigation with Double Microring Resonators and Data Encoding for Photonic NoCs,†IEEE Transactions on Very Large-Scale Integration (TVLSI), 2017.
I. Thakkar, S. Pasricha, “DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency and Restorable Endurance,†IEEE Transactions on Computer Aided Design (TCAD), 2017.
I. Thakkar, S. Pasricha, “3D-Wiz: A Novel High Bandwidth, Optically Interfaced 3D DRAM Architecture with Reduced Random Access Time,†IEEE International Conference on Computer Design (ICCD), Oct 2014.
S. Pasricha, I. Thakkar, “Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces,†Memory Architecture and Organization Workshop (MeAOW), Oct 2014. (Invited)
I. Thakkar, S. Pasricha, “A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses,†IEEE International Conference on Computer Design (ICCD), Oct 2015.
I. Thakkar, S. Pasricha, “Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures,†IEEE International Conference on VLSI Design (VLSI), Jan 2016.
S.V.R. Chittamuru, I. Thakkar, S. Pasricha, “Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures,†IEEE International Symposium on Quality Electronic Design (ISQED), Mar 2016. (Best Paper Award Finalist)
S.V.R. Chittamuru, I. Thakkar, S. Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs,†IEEE/ACM Design Automation Conference (DAC), Jun 2016.
I. Thakkar, S.V.R. Chittamuru, S. Pasricha, “A Comparative Analysis of Front-End and BackEnd Compatible Silicon Photonic On-Chip Interconnects,†ACM System Level Interconnect Prediction Workshop (SLIP), Jun 2016. (Best Paper Award)
I. Thakkar, S.V.R. Chittamuru, S. Pasricha, “Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers,†IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Aug 2016.
I. Thakkar, S.V.R. Chittamuru, S. Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2016.
I. Thakkar, S. Pasricha, “DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency,†IEEE International Conference on VLSI Design (VLSID), Jan 2017.
S.V.R. Chittamuru, I. Thakkar, S. Pasricha, “Analyzing Voltage Bias and Temperature Induced Aging Effects in Photonic Interconnects for Manycore Computing,†ACM System Level Interconnect Prediction Workshop (SLIP), Jun 2017.
I. Thakkar, S.V.R. Chittamuru, S. Pasricha, “Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling,†IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct 2017.
S.V.R. Chittamuru, I. Thakkar, S. Pasricha, “SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures,†IEEE/ACM Design Automation Conference (DAC), to appear, June 2018.
S. Pasricha, S.V.R. Chittamuru, I. Thakkar, “Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on- Chip,†ACM Great Lakes Symposium on VLSI (GLSVLSI), to appear, 2018.
Program of Study:
ECE561
CS545
ECE658
ECE554
ECE661
ECE548
ECE536
ECE573
