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Graduate Exam Abstract


sai vineel reddy chittamuru

Ph.D. Final
January 17, 2018, 2:30 pm - 4:00 pm
ECE Conference Room
Reliable, Energy-Efficient, and Secure Silicon Photonic Network-on-Chip Design for Manycore Computing

Abstract: Advances in technology scaling over the past several decades have enabled the integration of billions of transistors on a single die. Such a massive number of transistors has allowed multiple processing cores and significant memory to be integrated on a chip, to meet the rapidly growing performance demands of modern applications. These on-chip processing and memory components require an efficient mechanism to communicate with each other. Thus emerging manycore architectures with high core counts have adopted scalable packet switched electrical network-on-chip (ENoC) fabrics to support on-chip transfers. But with several hundreds to thousands of on-chip cores expected to become a reality in the near future, ENoCs are projected to suffer from cripplingly high power dissipation and limited performance. Recent developments in the area of silicon photonics have enabled the integration of on-chip photonic interconnects with CMOS circuits, enabling photonic networks-on-chip (PNoCs) that can offer ultra-high bandwidth, reduced power dissipation, and lower latency than ENoCs. There are several challenges that hinder the commercial adoption of these PNoC architectures. Especially, the operation of silicon photonic components is very sensitive to thermal variations (TV) and process variations (PV) that frequently occur on a chip. These variations and their mitigation techniques create significant reliability issues and increase energy costs in PNoCs. Furthermore, photonic components are susceptible to intrinsic crosstalk noise and aging, which demands higher energy for reliable communication. Moreover, contention in photonic waveguides as well as laser power distribution overheads also reduce performance and energy-efficiency. In addition, hardware trojans (HTs) in the electrical circuitry of photonic components lead to covert data snooping from shared photonic waveguides and introduces serious hardware security threats. To address these challenges, in this dissertation we propose a cross-layer framework towards the design of reliable, secure, and energy-efficient PNoC architectures. We devise layer-specific solutions for PNoC design as part of our framework: (i) we propose device-level enhancements to adapt to TV, and to mitigate heterodyne crosstalk and intermodulation effect induced heterodyne crosstalk; we also analyze aging in photonic components and explore its impact on PNoCs; (ii) at the circuit-level we propose PV-aware homodyne and heterodyne crosstalk mitigation mechanisms, a PV-aware security enhancement mechanism, and TV- and PV-aware photonic component assignment mechanisms; (iii) at the architecture-level we propose new application specific and reconfigurable PNoC architectures to improve photonic channel utilization, a laser power management scheme across components of PNoC architectures, and a reservation-assisted security enhancement scheme to improve security in PNoC architectures; and (iv) at the system-level we propose TV and PV aware thread migration schemes and application scheduling schemes that exploit adaptive application degree of parallelism (DoP). In addition to layer-specific enhancements, we also combine techniques across layers to create cross-layer optimization strategies to aggressively improve reliability and energy-efficiency in PNoC architectures. In our SPECTRA and LIBRA frameworks we combine system-level and circuit-level enhancements for TV management in PNoCs. In our ‘Island of Heater’ framework we combine system-level and device-level enhancements for TV management in PNoCs. We combine device-level and circuit-level enhancements for heterodyne crosstalk mitigation in our PICO and HYDRA frameworks. Our proposed BiGNoC architecture uses architectural-level enhancements and system-level application scheduling to improve its performance and energy-efficiency. Lastly, in our SOTERIA framework we combine circuit-level and architecture-level enhancements to enable secure communication in DWDM-based PNoC architectures.

Adviser: Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Yashwant K. Malaiya
Member 3: Anura Jayasumana
Addional Members: Sourajeet Roy

Publications:
[1] S. V. R. Chittamuru, S. Desai, S. Pasricha, “A Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Emerging Multicore Architectures," in GLSVLSI, May 2015 (Best Paper Award).
[2] S. V. R. Chittamuru, S. Pasricha, “Crosstalk Mitigation Mechanisms for High-Radix and Low-Diameter Photonic Crossbar Network Architecture," in IEEE Design and Test journal, June 2015.
[3] S. V. R. Chittamuru, S. Pasricha, "Improving Crosstalk Resilience with Wavelength Spacing in Photonic Crossbar-based Network-on-Chip Architectures," in MWSCAS, Aug. 2015.
[4] S. V. R. Chittamuru, S. Pasricha, "SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip," in VLSID, Jan. 2016.
[5] S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures," in ISQED, March 2016 (Best Paper Nomination).
[6] S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs," in DAC, June, 2016.
[7] I. Thakkar, S. V. R. Chittamuru and S. Pasricha, "A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects," in SLIP, June. 2016. (Best Paper Award)
[8] I. Thakkar, S. V. R. Chittamuru and S. Pasricha, "Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers," in NOCS, Aug. 2016.
[9] I. Thakkar, S. V. R. Chittamuru, and S. Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling," in ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2016.
[10] D. Dang, S. V. R. Chittamuru, R. Mahapatra, and S. Pasricha, "Islands of Heaters: A Novel Thermal Management Framework for Photonic NoCs," in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2017.
[11] S. V. R. Chittamuru, S. Desai, and S. Pasricha, "SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast Enabled Channel Sharing for Multicore Architectures,"in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 58, Feb. 2017.
[12] S. V. R. Chittamuru, I. Thakkar, and S. Pasricha, "Analyzing Voltage Bias and Temperature Induced Aging Effects in Photonic Interconnects for Manycore Computing," in International Workshop on System-Level Interconnect Prediction (SLIP), June. 2017.
[13] I. Thakkar, S. V. R. Chittamuru, and S. Pasricha, "Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling," in IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct. 2017.
[14] S. V. R. Chittamuru, I. Thakkar, and S. Pasricha, "HYDRA: Heterodyne Crosstalk Mitigation with Double Microring Resonators and Data Encoding for Photonic NoCs,"in IEEE Transactions on VLSI Systems (TVLSI), Aug. 2017.
[15] S. V. R. Chittamuru, I. Thakkar, and S. Pasricha, "LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip", in IEEE Transactions on Multi Scale Computing Systems(TMSCS), 2018. (Under Review)
[16] S. V. R. Chittamuru, D. Dang, S. Pasricha, and R. Mahapatra, "BiGNoC: Accelerating Big Data Computing with Application-
Specific Photonic Network-on-Chip Architectures", in IEEE Transactions on Parallel and Distributed Systems(TPDS), 2018. (Under Review)
[17] S. V. R. Chittamuru, I. Thakkar and S. Pasricha, "SOTERIA: Exploiting Process Variations to Enhance
Hardware Security with Photonic NoC Architectures," in IEEE/ACM Design Automation Conference (DAC), Jun. 2018. (Under Review)


Program of Study:
CS 420
ECE 661
ECE 658
ECE 561
ECE 554
ECE 514
CS 545
CS 520