Give


Graduate Exam Abstract


Ishan Thakkar

Ph.D. Preliminary

May 11, 2017, 1:30 pm - 3:00 pm

ECE Conference Room

Design and Optimization of Emerging Network-Memory Subsystems for Future Manycore Architectures


Abstract: With several hundreds of on-chip cores already becoming a reality, emerging manycore computing systems face major performance bottlenecks in their constituent subsystems, such as the on-chip communication, core-to-memory interface, and main memory subsystems. With recent advances in silicon photonics, photonic networks-on-chip (PNoCs) and core-to-memory photonic interfaces have emerged as scalable communication fabrics to enable high-bandwidth data transfers in emerging manycore systems. However, these interconnection subsystems still face many challenges due to thermal and process variations, crosstalk noise, and high overheads of laser power generation, coupling, and distribution, all of which negatively impact reliability and energy-efficiency. Along the same lines, with the advent of through-silicon via (TSV) technology, 3D-stacked DRAM architectures have emerged as small-footprint main memory solutions with relatively low per-access latency and energy costs. However, the full potential of the 3D-stacked DRAM technology remains untapped due to thermal- and scaling-induced data instability, high leakage, and high refresh rate problems along with other challenges related to 3D floorplanning and power integrity. Recent advances have also enabled Phase Change Memory (PCM) as a leading technology that can alleviate the leakage and scalability shortcomings of DRAM. But asymmetric write latency and low endurance of PCM are major challenges for its widespread adoption as main memory in future manycore systems. To overcome all of these challenges, the main contribution of my thesis is a framework for the design and optimization of emerging network-memory subsystems for future manycore computing systems. The proposed framework synergistically integrates layer-specific enhancements towards the design and optimization of emerging main memory, PNoC, and inter-chip photonic interface subsystems. The proposed framework includes the following subsystem-specific solutions: (i) for the design and optimization of 3D-stacked DRAM based main memory subsystems, we propose 3D-floorplan aware folded bank architectures at the microarchitecture level, along with power-integrity aware concurrence-maximizing scheduling schemes, and a per-tier all-bank refresh method; (ii) for the design of PCM-based optimized main memory subsystems, we propose a write latency improving technique along with a write endurance restoring technique at the architecture level; (iii) for core-to-memory photonic interfaces, we propose package-driven thermal stabilization and platform selection; (iv) for PNoCs, we propose optimization of cross-platform design parameters at the device level, laser power management and reconfigurable architectures at the architecture level, along with variation aware heterodyne and homodyne crosstalk mitigation techniques and optimization of signaling method at the system level. In addition to subsystem-specific enhancements, we also combine enhancements across subsystems to more aggressively improve the performance, energy-efficiency, and reliability for future manycore architectures.

Adviser: Dr Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Dr Wim Bohm
Member 3: Dr Kevin Lear
Addional Members: Dr Anura Jayasumana

Publications:
Research Book Chapters:

[BC1] Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan Thakkar, “Enhancing Process Variation Resilience in Photonic NoC Architectures”, to appear, Optical Interconnects for Computer Systems, River Publishers, 2016.


Peer-Reviewed Journal Publications:

[J5] Ishan Thakkar, Sudeep Pasricha, “DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency and Restorable Endurance”, submitted for review to IEEE Transactions on Computer Aided Design (TCAD), 2017.
[J4] Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, “HYDRA: Heterodyne Crosstalk Mitigation with Double Microring Resonators and Data Encoding for Photonic NoCs”, submitted for review to IEEE Transactions on Very Large Scale Integration (TVLSI), 2017.

[J3] Ishan Thakkar, Sudeep Pasricha, “3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead”, IEEE Transactions on Multi-Scale Computing Systems, vol. 1, no. 3, pp. 168-184, Sept 2015.

[J2] Ishan Thakkar, Sudeep Pasricha, “3D-WiRED: A Novel WIDE I/O DRAM With Energy-Efficient
3-D Bank Organization”, IEEE Design & Test, vol. 32, no. 4, pp. 71-80, Aug 2015.

[J1] Ishan Thakkar, Kevin L Lear, Jonathan Vickers, Brian Heinze and Kenneth Reardon, "A plastic total internal reflection photoluminescence device for enzymatic biosensing", Lab Chip, vol. 13, no. 34, pp. 4775-4783, Dec 2013.


Peer-Reviewed Conference Publications and Presentations (20-30% acceptance rate):

[C10] Ishan Thakkar, Sudeep Pasricha, “DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency”, IEEE International Conference on VLSI Design (VLSID), to appear, Jan 2017.
[C9] Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling", ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2016. (26% acceptance rate)

[C8] Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, “Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers”, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Aug 2016.

[C7] Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, “A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects”, ACM System Level Interconnect Prediction Workshop (SLIP), Jun 2016. (Best Paper Award)

[C6] Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs”, IEEE/ACM Design Automation Conference (DAC), Jun 2016.

[C5] Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, “Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar 2016. (Best Paper Award Finalist)

[C4] Ishan Thakkar, Sudeep Pasricha, “Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures”, IEEE International Conference on VLSI Design (VLSI), Jan 2016.

[C3] Ishan Thakkar, Sudeep Pasricha, “A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses”, IEEE International Conference on Computer Design (ICCD), Oct 2015.

[C2] Sudeep Pasricha, Ishan Thakkar, “Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces”, Memory Architecture and Organization Workshop (MeAOW), Oct 2014.

[C1] Ishan Thakkar, Sudeep Pasricha, “3D-Wiz: A Novel High Bandwidth, Optically Interfaced 3D DRAM Architecture with Reduced Random Access Time”, IEEE International Conference on Computer Design (ICCD), Oct 2014.


Peer-Reviewed Conference Poster Presentations:

[CP5] Ishan Thakkar, “Design and Optimization of Emerging Network-Memory Subsystems for Future Manycore Architectures”, in the PhD Forum at the ACM/IEEE Design Automation Conference (DAC), to appear, June 2017.

[CP4] Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling", ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2016. (26% acceptance rate)

[CP3] Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, “Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers”, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Aug 2016.

[CP2] Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs”, IEEE/ACM Design Automation Conference (DAC), Jun 2016.

[CP1] Ishan Thakkar, Sudeep Pasricha, “A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses”, IEEE International Conference on Computer Design (ICCD), Oct 2015.


Research Posters (Non-Conference):

[P2] Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, “A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects”, ACM/IEEE Design Automation Conference Work in Progress (WIP), Jun 2016.

[P1] Ishan Thakkar, Sudeep Pasricha, “Improving the Performance and Power Efficiency of Memory with 3D Stacking and High-Bandwidth Optical Interfacing”, CSU Ventures Innovation Forum,
Apr 2016.


Program of Study:
ECE554
ECE661
ECE658
CS545
ECE561
ECE536
ECE699
ECE799