Graduate Exam Abstract

sai vineel reddy chittamuru

Ph.D. Preliminary
December 12, 2016, 1:00 pm - 3:00 pm
ECE Conference Room C101 B
Reliable and Energy-Efficient Silicon Photonic Network-on-Chip Design for Manycore Architectures

Abstract: On-chip communication is widely considered to be one of the major performance bottlenecks in emerging many-core systems-on-chip (SoCs). With recent advances in silicon photonics, photonic networks-on-chip (PNoCs) are being considered as a viable option for communication in emerging CMPs as they can enable higher bandwidth and lower power data transfers compared to traditional electrical NoCs. However, the operation of silicon photonic components is very sensitive to thermal and process variations that frequently occur on a chip. These variations and their mitigation techniques create significant reliability issues and increase energy costs in PNoCs. Moreover, contention in photonic waveguides as well as laser power distribution overheads also reduce performance and energy-efficiency. To address these issues, as a part of our research we propose a cross-layer framework which integrates system-level, architecture-level, and circuit-level enhancements towards the design of reliable and energy-efficient PNoC architectures.

Adviser: Prof. Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Prof. Yashwant K. Malaiya, CS
Member 3: Prof. Anura Jayasumana, ECE
Addional Members: Prof. Sourajeet Roy, ECE

[1] S. V. R. Chittamuru, S. Desai, S. Pasricha, “A Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Emerging Multicore Architectures," in GLSVLSI, May 2015 (Best Paper Award).
[2] S. V. R. Chittamuru, S. Pasricha, “Crosstalk Mitigation Mechanisms for High-Radix and Low-Diameter Photonic Crossbar Network Architecture," in IEEE Design and Test journal, June 2015.
[3] S. V. R. Chittamuru, S. Pasricha, "Improving Crosstalk Resilience with Wavelength Spacing in Photonic Crossbar-based Network-on-Chip Architectures," in MWSCAS, Aug. 2015.
[4] S. V. R. Chittamuru, S. Pasricha, "SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip," in VLSID, Jan. 2016.
[5] S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures," in ISQED, March 2016 (Best Paper Nomination).
[6] S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs," in DAC, June, 2016.
[7] I. Thakkar, S. V. R. Chittamuru and S. Pasricha, "A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects," in SLIP, June. 2016. (Best Paper Award)
[8] I. Thakkar, S. V. R. Chittamuru and S. Pasricha, "Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers," in NOCS, Aug. 2016.
[9] I. Thakkar, S. V. R. Chittamuru, and S. Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling," in ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2016.
[10] D. Dang, S. V. R. Chittamuru, R. Mahapatra, and S. Pasricha, "Islands of Heaters: A Novel Thermal Management Framework for Photonic NoCs," in IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2017.

Program of Study:
CS 420
CS 520
CS 545
ECE 514
ECE 554
ECE 561
ECE 658
ECE 661