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Graduate Exam Abstract


Pramit Rajkrishna

M.S. Final

February 5, 2016, 9:00 am - 11:00 am

ECE Conference Room

AN INTEGRATED VARIATION-AWARE MAPPING FRAMEWORK FOR FINFET BASED IRREGULAR 2D MPSOCs IN THE DARK SILICON ERA


Abstract: In the deep submicron era, process variations and dark silicon considerations have become prominent focus areas for early stage NoC design synthesis. Additionally, FinFETs have been implemented as promising alternatives to bulk CMOS implementations for 22nm and below technology nodes to mitigate leakage power. While overall system power in a dark silicon paradigm is governed by a limitation on active cores and inter core communication patterns, it has also become imperative to consider process variations in a holistic context for irregular 2D networks-on-chip (NoCs). Additionally, manufacturing defects induce link failures, inducing resultant irregularity in the NoC topology and rendering conventional minimal routing schemes for regular topologies inoperable. In this thesis, we propose a holistic process variation aware design time synthesis framework (HERMES) that performs computation and communication mapping while minimizing energy consumption and maximizing Power Performance Yield (PPY). The framework targets a 22nm FinFET based homogenous NoC implementation with design time link failures in the NoC fabric, a dark silicon based power constraint and system bandwidth constraints for performance guarantees, while preserving connectivity and deadlock freedom in the NoC fabric. Our experimental results show that HERMES performs 1.32x better in energy, 1.29x better in simulation execution time and 50% better in PPY statistics, over other state-of-the-art proposed mapping techniques for various SPLASH2 and PARSEC parallel benchmarks.

Adviser: Prof. Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Prof. Patrick Burns, VP (IT), Mechanical Engineering
Member 3: Prof. Anura Jayasumana, Electrical and Computer Engineering
Addional Members: N/A

Publications:
N/A


Program of Study:
CS 420 - Intro-Analysis of Algorithms
ECE 450/451 - Digital System Design
ECE 531 - Engineering Risk Analysis
ECE 554 - Computer Architecture
ECE 561 - Design of Embedded Systems
ECE 571/575 - VLSI System Design
GRAD 511 - High Performance Computing and Visualiz
GRAD 580A1 - STEM Communication