Graduate Exam Abstract

Nishit Kapadia

Ph.D. Final

April 29, 2015, 3:00 pm - 5:00 pm

Room: LSC 378


Abstract: As a result of semiconductor technology scaling persisting over the last five decades, chip designers are today faced with the task of managing over a billion on-chip transistors. With feature sizes of no more than a few tens of nanometers in contemporary technologies, several undesirable phenomena at such nanoscale geometries have significantly complicated System-on-Chip (SoC) design. These phenomena include: (i) an increased influence of process variations that has introduced considerable unpredictability in circuit- behavior; (ii) a lowering of the critical charge of logic- and memory-cells that has given rise to elevated levels of soft-errors; (iii) a steep rise in power-densities due to higher transistor-densities, that has introduced the problem of dark- silicon, where a significant portion of the chip is required to be shut down at any given time; (iv) circuit aging that has increased significantly because of higher severity of aging factors such as electromigration and bias temperature instability (BTI) in circuits fabricated in advanced technology nodes; and (v) high voltage drops in the power delivery network (PDN) that have worsened due to the shrinking widths of on-chip interconnects. Additionally, even though the design complexity has risen exponentially, the time-to-market window for design companies has not changed markedly. Despite the numerous daunting challenges faced by the semiconductor design community, each new generation of SoCs are expected to meet higher and higher performance demands. Therefore, there is an urgent need for holistic automated system-level design tools that produce feasible and optimized design solutions efficiently while satisfying application and platform constraints. As a lot more transistors become available to designers with every new technology node, we are witnessing a trend of increasing number of processing cores on the semiconductor die. With tens to hundreds of cores being integrated on emerging multicore SoCs, network- on-chip (NoC) based communication architectures have been found to be more suitable compared to the traditional bus-based communication architectures. Also, the recently evolved paradigm of 3D stacking of ICs has opened up new avenues for extracting higher performance from future systems by stacking multiple layers of cores and memory. In this thesis, we propose design-time optimization frameworks for synthesis of 2D and 3D NoC-based multicore SoCs. We present novel algorithms and heuristics for application- mapping, voltage-island partitioning, and NoC routing path allocation to optimize metrics such as communication and computation power and energy, chip-cooling power, voltage-drops in the PDN, design-yield, and energy-delay- squared product (ED2P), while satisfying temperature, PDN, and performance constraints. In addition, to address the critical need for system-level solutions that can simultaneously and adaptively manage the constraints imposed by dark silicon, process variations, soft- error reliability, and lifetime reliability, we propose run-time frameworks for OS-level adaptations based on the circuit-level characteristics of multicore SoCs. Experimental results show that the techniques proposed in this thesis produce design solutions that provide much better overall optimality while considering multiple optimization metrics pertinent to modern semiconductor design.

Adviser: Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member: Michelle Strout
Member 3: H.J. Siegel
Addional Members: Anura Jayasumana

• N. Kapadia, S. Pasricha, “VISION: A Framework for Voltage Island Aware Synthesis of Interconnection Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2011, May 2011.
• N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands”, IEEE International Conference on VLSI Design (VLSID), January 2012.
• N. Kapadia, S. Pasricha, “A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands”, Integration, the VLSI Journal, June 2012.
• N. Kapadia, S. Pasricha, “VERVE: A Framework for Variation-Aware Energy Efficient Synthesis of NoC-based MPSoCs with Voltage islands”, IEEE International Symposium on Quality Electronic Design (ISQED), March 2013.
• N. Kapadia, S. Pasricha, “A Co-Synthesis Methodology for Power Delivery and Data Interconnection Networks in 3D ICs”, IEEE International Symposium on Quality Electronic Design (ISQED), March 2013.
• N. Kapadia, S. Pasricha, “Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize Yield”, IEEE International Conference on VLSI Design (VLSID), January 2014.
• N. Kapadia, S. Pasricha, “PRATHAM: A Power Delivery-Aware and Thermal-Aware Mapping Framework for Parallel Embedded Applications on 3D MPSoCs", IEEE International Conference on Computer Design (ICCD), October 2014.
• N. Kapadia, S. Pasricha, “VARSHA: Variation and Reliability-Aware Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era", Design Automation and Test in Europe (DATE) conference, March 2015.
• N. Kapadia, S. Pasricha, “A System-Level Co-Synthesis Framework for Power Delivery and On-chip Data Networks in Application-Specific 3D ICs" IEEE Transactions on Very Large Scale Integration Systems (TVLSI), February 2015.

• N. Kapadia, S. Pasricha, “ARTEMIS: An Aging-Aware Run-Time Resource Management Framework for 3D CMPs in the Dark-Silicon Era”, under review.

Program of Study:
ECE 661
ECE 658