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Graduate Exam Abstract


YONG ZOU

Ph.D. Qualifying

November 8, 2012, 1:00 - 2:30

ENgineering B101

N/A - qualifying exam


Abstract: qualifying exam

Adviser: Sudeep Pasricha
Co-Adviser: N/A
Non-ECE Member:
Member 3: Thomas Chen, Electrical and Computer Engineering
Addional Members: Anura Jayasumana, Electrical and Computer Engineering

Publications:
Book Chapters: S. Pasricha, Y. Zou, "Hybrid Partially Adaptive Fault Tolerant Routing for 3D Networks-on-Chip", to appear, Topics in Embedded Systems, edited by CRC Press, 2012

Journal Articles: Y. Zou, Y. Xiang, S. Pasricha, "Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors", IEEE Embedded System Letters, 4(2), Jun 2012. Y. Zou, S. Pasricha, "NARCO: Neighbor Aware Turn Model Based Fault Tolerant Routing for NoCs", IEEE Embedded System Letters, Vol. 2, No. 3, Sep 2010.

Conference Papers: Y. Zou, Y. Xiang, S. Pasricha, "Analysis of On-chip Interconnection Network Interface Reliability in Multicore Systems", IEEE International Conference on Computer Design (ICCD), Oct. 2011. S. Pasricha, Y. Zou, "A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip", IEEE International Symposium on Quality Electronic Design (ISQED 2011), Santa Clara, CA, Mar 2011 S. Pasricha, Y. Zou, "NS-FTR: A Fault Tolerant Routing Scheme for Networks on Chip with Permanent and Runtime Intermittent Faults", IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, Jan 2011 S. Pasricha, Y. Zou, D. Connors, H. J. Siegel, "OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip", Proc. IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),Scottsdale, AZ, Oct 2010


Publications to be Reviewed:
Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors

OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip

Program of Study:
ECE561
ECE658
ECE674
MATH510
STAT520
ECE799
N/A
N/A