.: About
Last Updated: 05/09/07.
All the required end-of-year documents are posted to Documentation section.
Luke Ciavonne and Mehdi Mehrpartou have joined the
project this semester as Pat Kusbel has continued on to graduate school.
Coming soon will be a bio for Luke and Mehdi in the column to the left.
Luke will be working mainly on verilog synthesis for the analog
daughterboard while Medhi will initially be doing hardware verification. We
welcome there highly skilled talents to the team and look forward to
getting a working prototype by the end of the semester. I will be
continuing Linux development in addition to working closely with luke on
verilog synthesis. The goal of this project is to design a control and
acquisition system to interface to Dr. Reising's "Water Vapor
Profiling Radiometer". We are aiming to optimize size, power
consumption and cost. Pat Kusbel and Elliot Buller are the team members for
this project. Elliot is primarily responsible for software, and Pat is
primarily responsible for the hardware design, though he is consulting a
bit on the software architecture. The project consists of designing a PC104 compatible data
acquisition and control sytem. There are 2 pieces: a data acquistion card
that we are designing and a processor board that we'll buy off the shelf.
Originally, the acquisition card would have all been controlled by a CPLD,
however, due to logic constraints (we ran out of CPLD gates), we upped this
to an FPGA, a Xilinx
Spartan 3E to be exact. This board will connect to an external system
board computer (SBC) via the PC104 expansion bus. The SBC chosen was the TS7300 from
Technologic Systems. We bought a board for evaluation and testing, and
Elliot has set up a sweet demo of it. Just push the Live Demo button to the
left and you'll be taken to a webpage driven by the TS7300 (provided the
network at Elliot's house is up)! This project has something for everyone:
software, digital design/synthesis, analog design, and RF interfacing. Board Specs: 4 ADC's: 2 for monitoring 6 RTD's, 1 for measuring the
output of the RF detector, and 1 for measuring the angle (inclination) of
the radiometer as well as the current to the LNA and IF amps. 1 DAC for adjusting the LNA gate voltage. Power distribution system: various voltage regulators for
generating the requisite voltages for use on the board as well as for the
RF circuits. Also some circuitry for dynamically adjusting LNA VDD (this
was a pretty clever circuit that we designed, if we do say so ourselves). FPGA for controlling the board, buffering data, providing
control signals to the RF subsystem, and communicating with the host via
PC104. As we said, we're using the Spartan 3E, 500K gates in a 22mm x 22mm
PQ208 package. We're rapidly running out space, though, so we may change
this to a BGA which is 19x19. However, that makes routing much more
difficult and might necessitate a 6-layer board (we're currently using 4),
so we're trying to stay with a QFP. .: Useful Links
Here's some very useful links for PCB design. Organizations/Sites
Files
and Documents
And last but not least, a hearty thanks
to all of those that have helped make this project happen! .: Current
Project Status
4-29-2007 This is the final entry for this semester. We must admit, it
was wild ride. We got an incredible amnount of work done in a short amount
of time and have a system that we're pretty proud of. We ended up coming in
3rd place E-Days, and that's out of the way. We also gave a presentation at
the Industrial Advisory Board that went very well and we're also pleased
with that. But most importantly, our customer, Dr. Reising, is happy with
his board. It's very satisfying to know you've met or exceeded your
customers expectations. For those that are interested, our final report is available
in the documents section, or you can just click here. Problem with
a big project is you end up with a big report as well. This was painful to
write! Another very positive thing came out of all of these demo's
and presentations: we've attracted a lot of interest in our project and in
radiometry in general, and we've managed to pick up some exceptional talent
for next semester as a result. Mehdi Mehrparto, recepient of this years
"Oustanding Junior" award, and Luke Ciavonne, another very sharp
junior, will be joining us next semester to try and finish this thing off.
Pat will be managing the project as part of his master's work, and Elliot
will be finishing his degree next semester and working on this project for
Sr. Design as well. We've got a real "A" team for next semester
and we're excited about what we can accomplish. Here's the tasking as it stands now: *hardware verification and debug (power system
debug/testing,amplifier/signal conditioning testing/debug, and ADC debug):
Mehdi As you can tell, we're still short one software person. If
you know someone that's very motivated, very sharp, and wants to work on
this project for senior design next year, have them send an application to
Dr. Reising. And that, as they say, is that. 4-9-2007 We got the boards back from AAPCB today. They look great,
just perfect. Here's the front and back assembled board. The wires coming
out the bottom are used to power the board right now. We got the wrong
power connectors from Digikey (my fault), so we're using regular wire right
now until we get the right connectors in. But anyhow, as you can see from
the photo's, AAPCB did a fantastic job! Even better, the board works! We turned it on and first
checked all of the voltages (after making sure that no parts were getting
warm). Switcher voltages were dead-on where we wanted them, which was a bit
of shock as we figured there'd be some resistor tweaking there. So after
verifying all of the voltages, we probed some of the FPGA signals to see if
it was working. CCLK is the clock signal the FPGA generates when it is
trying to configure itself from the onboard ROM. If CCLK works, then that
means that the FPGA is trying to boot up. So we probed CCLK and sure
enough, we saw a nice clock there. We then hooked up the board to the Xilinx JTAG tool (iMPACT,
and yes, that is supposed to be a lower-case 'i'), and that's where we
encountered our first, and hopefully only, problem. None of the parts were
showing up on the boundary scan. Since CCLK was being generated, we knew
that the FPGA was working, so we figured it was either a signal issue or
possibly a bad flash since it was last in the boundary scan chain. So we used the debug mode of iMPACT to wiggle the JTAG lines
individually. Everything looked good up to the FPGA so we probed the flash,
and that's where we found the problem. TCK was routed to TDI and
vice-versa. You can see it on the schematic,
page 4 grid B-2. TDI is crossed with TCK. Ugh, that's a lousy mistake to
make... The fix was pretty simpled: we cut those 2 traces and
swapped them with wires. You can see our handiwork on the back picture
shown above. It's the red wire coming from a via to the flash. The other
wire is hard to see, but it's there. Fortunately, this mistake only affects
JTAG. JTAG is only used for debugging and for programming the flash. In
"normal" operation, these signals are never used, so they won't
have a functional impact on the board itself. It's really more of a
nuisance, and we're actually quite irritated that we made this particular
mistake since we had multiple people review the schematic. Oh well, as they
say in France, C'est la vie... Anyhow, after swapping those 2 nets back to where they
belong, the FPGA and flash immediately showed up on boundary scan ready to
be programmed. What a relief! After over 500 hours of work, we were quite
concerned that we may have overlooked something big. Fortunately, we
didn't, and so far all of the major pieces are working. We did some quick power consumption measurements and the
board clocked in at .36W. That gives us a net power consumption of 1.85 W
(TS7300) + .36 W (board) = 2.21 W. Well under the 3 W design goal we had.
Now this will go up some once we have "real" FPGA code in and the
radiometer functioning for real, but we'll still come in well under the 3 W
design goal we started with. Things are looking up. Next tasks: E-Days demo, populate the
missing parts (PC104 connector, 2 power connectors, and the MACOM pin-diode
drivers), and test out the analog circuits. 4-5-2007 We got everything staged and ready to go. We put the labels
that AAPCB made for us on the component bags from Digikey so that it would
be easy for them to identify the parts. In the process of doing this, we
found a couple mistakes: 2 connectors were wrong due to a goof on my part
where I put the wrong part # in my parts database (75443 vs 75553, which
resulted in a vertical connector instead of a right-angle connector), and
one header was missing. We called Jim, one of the engineers at AAPCB, and
he changed the order so that those parts won't be placed, so that's not a
big deal. However, the components are important: they are the power
connectors for the board! We'll order them tonight from Digikey and order
them 2nd day so we can get the parts by Monday. That way we'll be able to
place them by hand when the boards get back. The folks at AAPCB have really gone out of their way to help
us out. Jim, one of the engineers we've been working with at AAPCB, lives
in Loveland. He called me today and volunteered to meet in the
Loveland/Longmont area to drive the parts down to AAPCB himself, which
saves me a 2 hour round-trip drive. How's that for service with a personal
touch! These guys are just outstanding. If you ever need stuff assembled,
give the folks at AAPCB a call first. All that's left now is to meet with Jim tomorrow to hand off
the parts, and hope that everything goes smoothly. If it does, we'll get
boards back sometime Monday. 4-3-2007 Looks like things are coming together. I received the flash
parts this morning, so those are ready to go. I placed the order for the
MACOM pin-diode drivers last night, and we may get them by Wednesday which
would be nice because then we can have AAPCB place them for us. We also received the Eval board from Xilinx today so we can
actually get a head start on some of the Verilog programming of the FPGA.
It'd be cool to be able to use our actual board for the E-Days dog &
pony show, and the eval board gives us a chance to make that happen. The only things we're waiting on now are the Digikey order
and the FPGA. If those come on time, then we'll definitely have a board
ready for next Tuesday. 4-2-2007 We finally taped out today. It was a real struggle this past
week trying to get all of the stars to line up just right. First off, some
of the parts that were available when we designed the board were no longer
available. This required 2 last minute footprint changes so that we could
become compatible with alternate part. Then we had some issues with emails
getting through from Advanced Circuits. Apparently, an email filter thought
it was spam and was deleting them. Everything finally got cleared up around
11:00 am, but that was just more time lost. Anyhow, we finally got the boards out today, and most of the
parts are all ordered. MACOM wouldn't sample us the pin-diode driver, so
we'll have to order them from Avnet. We won't get them in time for
assembly, so we'll have to solder them by hand. Not a big deal, they're in
a big SOIC package with 1.27mm pitch, so they'll be easy to solder by hand.
We also had a difficult time getting the FPGA and flash. NuHorizon was
reworking their website this weekend, and when I went to order the parts,
the FPGA didn't show up in the parts search. I ordered just the flash for
$12.10, but they slapped on a $12.90 minimum cost charge. That didn't show
up on the website until after the order was placed. I called them this morning
to straighten this out since it's ridiculous that the minimum charge was
more than the cost of my part. At the minumum they should have just given
me two flashes. Anyhow, after a couple of phone calls, they were able to
cancel the order. In the meantime, Hai Chau, a components engineer at
Qualcomm, was able to track down some samples for me of both the FPGA and
the flash. Bonus! So we were able to get those parts for free. Thanks Hai,
we owe you a big one. Our saga continues: in the process of changing the
footprints that we mentioned above, I goofed and didn't create the paste
mask files. Those are needed by the assembly house to create the solder
stencil for the paste. Think of the stencil as a sheet of metal with holes
in it where the solder should stick to the board. The assembly house
creates the stencil based on the paste mask, places the stencil over the
board, drops some paste on it, wipes the excess paste off, and then removes
the stencil leaving solder paste on the pads ready to have components placed
on them. The stencil controls where the solder goes as well as thickness,
etc. Well, when I created the gerbers for round 2, I didn't check the boxes
to create the paste mask. No paste mask = no stencil = no assembly. So I regenerated the gerbers, this time with the paste mask
files created. This is when my day went south very quickly... The newly
generated gerbers were *different* than the ones I generated Saturday
night. That scared me to death, and I about threw up. If the gerbers were
different, then that meant the board had somehow changed. So I either
inadvertently changed the board between Saturday night and today, or I
generated the wrong gerbers Saturday night. Neither result was good. I
called Scott at Advanced Circuits in a bit of a panic, and thankfully, they
hadn't started on the board yet. I asked him to hold off for a bit so I
could try to unravel this mess, and he said no problem. Did I mention how
great Advanced Circuits has been? Anyhow, I called my wife and had her
regenerate a set of gerbers at home thinking that I may have had the wrong
project files on my laptop. She generated them and sent them to me, and
those gerbers matched the ones from my laptop. Since the DRC passed and the
generated files from both machines matched, I have some faith that these
are correct, so these new files are the ones I sent to Advanced Circuits.
After I sent them off, I did a quick comparison and the old and new files
look the same in a gerber viewer, so I'm not sure what happened. Anyhow, the boards are being fabbed now, and will be ready
Thursday night. The BOM order was placed today from Digikey and wil be here
Thursday, so we'll take the parts + samples and drop them off at AAPCB (the
assembly house). They'll start assembling Friday morning, and as I had
mentioned, they actually cut us a break on the turn: they gave us a 1-day
turn for the price of a 2-day turn, so we'll have the boards back Monday
night, just in time for E-Days on Tuesday. Thanks to Lydia and AAPCB, we
appreciate it! We did have one major shock: the cost of assembly. It was
about 3x what we thought it would be. It ended up costing ~$900 for 1
board, which was a lot more than the $300 we estimated. On the AAPCB
website, they said it was $245 for 200 parts (including BGA/DFN). However,
our component count was well outside the 200 listed, we were actually at
500+, and we had quite a few fine-pitch/difficult parts (1 1mm pitch BGA
with a bunch of .5mm pitch DFN's). They were very accommodating of us
though and worked real hard to help us make this project happen. They gave
us $300 off the price and a 1-day turn for the price of a 2-day turn so
that we could get the board in time for E-Days. Iit was still a long ways
off the $300 mark we had estimated though, and the one area where we grossly
underestimated what it would really cost. I really should've contacted
AAPCB first to get a real estimate instead of just guessing, but I was so
busy trying to finish the board that it slipped my mind. On another front, Hai helped get some FPGA eval boards.
They'll be used for a related project at Qualcomm, but we'll also be able
to use them for this project as well. This will help us get a jump-start on
FPGA development. We should be getting those late this week. If all goes
according to plan, then we get some basic FPGA functionality going this
week on the development boards and come monday, we take the same FPGA code
and load it into our board. If all of the stars are lined up correctly,
then for E-Days next tuesday, we'll actually have something functional to
demo. 3-29-2007 Hooray, we finally passed
the Design for Manufacturing checks! This means the board is done! For the
past couple of days, we've been trying to get the board to pass the design
checks at FreeDFM
before submitting the final gerbers for manufacturing. For various reasons,
we were failing some checks. Some failures were due to improper settings,
such as insufficient inner clearance (software setting). Inner clearance
was .010" (10 mils). Somehow, I turned that into .1mm instead of
.254mm. Doh! FreeDFM is a wonderful tool. It's provided as a free service
by Advanced Circuits, our board vendor. Our first
pass through FreeDFM had a TON of errors. After a couple of days of
tweaking, we finally got a clean bill of health today. Scott Walsh is the regional sales manager at Advanced
Circuits. He was extremely pleasant and helpful, which was quite
refreshing. I was afraid that since we are not going to be a
"big" order, that we would get second-class treatment. That certainly
wasn't the case, and I can't say enough about the caliber of this company.
Highly recommended! Anyhow, I spoke with Scott today after we finally
passed the DFM checks to discuss the cost. He cut us a 50% discount, which
amounts to $360 total cost for 3 boards with HAL solder, or $500 with gold
immersion. I prefer gold immersion since we have a lot of testpoints and
some unpopulated pads that will be exposed, but since the boards are Dr.
Reisings, it's his call. Here's the latest, and final, drawings of the board. First
the 3D front and back. Here's the CAD drawings: top, internal, bottom, and composite. On the documents
page, you'll be able to find links to the final schematics as well as the
gerbers. So the board is finally done, but we still have to get it
assembled. We've got lots of part samples ordered and received which will
cut way down on our BOM, but we still need to order the rest of our parts.
We'll finish that tomorrow, and we'll also call AAPCB tomorrow to get the
assembly quote. As we mentioned before, they have a special this month, so
worst case, it shouldn't cost more than ~$300. Oh, and while we're on the topic of assembly, we'll throw a
quick plug in for Coilcraft. They're an inductor vendor, and they have a
most generous student
sample policy which we certainly appreciate and are grateful for. Use
them whenever you can, especially in the "real world". If more
companies had policies like this, it'd be more feasible and cost-effective
to do PCB design in school. 3-26-2007 First, we gave the board a new name. "Control and
Computing System for a Miniaturized Water Vapor Profiling Radiometer"
is a bit verbose and very boring. So we did what all good engineers do in
these situations: came up with an acronym! CADAS, or Control and Data
Acquisition System. Sounds much more impressive :) The official name, at
least as it will appear on the silk screen, is the "P&E CADA
System II". P&E is Pat & Elliot (us, the designers), and since
this is the second iteration of the control system, it gets a numeral II.
We like it. The P&E CADA System II sounds neat, something you might
make you take a second look, or even better, buy! Second, we were going to place 64MB of DDR ram on the board.
We had some samples from Micron (free) all set to go, but ran into a
packaging problem. We were using a 208 QFP part, which is big (27mm x
27mm). There weren't enough I/O's available to place extra stuff (such as
spare signal headers or RAM), so we upsized the package to the 256 pin BGA.
Everything was fine until we went to place the RAM and that's when we found
the major problem: the RAM is 1.8V, but all of the signalling on our board
is 3V. The FPGA has separate power rails for each bank, so this in and of
itself wasn't a problem since we could just connect one bank of the I/O's
(there are 4 total) to 1.8V. The problem came in the fact that we need 42
bi-directional pins, and with the 256 BGA package, each bank has at most 38
pins that are bi-directional (there's more pins, but some are dedicated for
other uses or are fixed as input-only pins). To make this work, we'd have
to use pins from 2 banks, and that meant that we'd have to configure 2
banks to run at 1.8V. This would for all intents and purpose render the
other 30 some pins useless to us since we can't use them on the 3.3V I/O's
used by the rest of the board. This would have made us short again on pin
count. We had a few options available. Option one was to place the
part anyway, use one bank at 1.8V, and use 4 pins of the other bank for
slow-moving lines (like the chip-select) with an external pull-up to 1.8V.
We would then configure those pins to be open-drain pins with the external
pull-up providing the drive to 1.8V. The idea is that we would configure
the bank with the 4 pins for 3.3V so we could use it with the rest of the
board but maintain supply compatibility with the 1.8V RAM. This isn't ideal
since the interface standard the pins would be configured for would be
different than the 1.8V bank, which is why we would try to use those for
"slow" signals like chip-selects. If we had time and the ability
to experiment, we might try it, but we don't have time and this path was
too risky, so we discarded this option. Another option was to upsize the package. The 320-pin BGA
part had enough pins on a single bank. However, no vendors had these parts
in stock, and all had a minimum 4-week lead time to get us one. By that
time, the semester will be over, so this option was discarded. This left option 3: leave the RAM off. So that's what we
did. We did keep the BGA since it made routing some parts of the board
easier due to there being more space (the BGA is 19mm x 19mm as opposed to
the 27mm x 27mm QFP). We also had enough pins to add 2.54mm pitch headers
to use for debugging and future expansion, so that was nice. Major milestone met: we finally finished routing the board.
Here's the 3D views of the front and
back. Here's the CAD views of the top layer, internal layer (signal and power),
bottom layer, and the composite view. The composite looks most
impressive :) However, this took an incredible amount of time. All day and
all night friday, saturday and sunday was spent routing and putting the
finishing touches on the board. The only breaks came between 5 am and 10 am
for sleep, after which we started at it again. We're hoping it works as
good as it looks. We're now in the throes of design rule checking with
Advanced Circuits (or board fabrication vendor). They have a nice online
design rule check tool, and it did catch some problems that we're currently
fixing. Hopefully, that will be all take care of by tomorrow, and then
we'll be set to order the board. We spoke with them last friday and they
quoted us $300 for the board. Because we moved to a BGA, we had to change
the minimum line spacing to 5/5 (5 mil trace with 5 mil space). That added
~$100 total cost, but it was well worth it. Going to 5/5 from 8/8 made
routing *much* easier, and at this stage of the game, we need everything we
can that will make our life easier. Important tip and lesson learned: it's
well worth the extra money spent to go with smaller trace/space. We spent a
lot time trying to work with bigger traces/spaces, time that we wouldn't
have spent if we had just gone with 5/5 from the beginning. Time is money,
so in the end, it actually would have been cheaper for us if we had just
started with 5/5 in the first place. We now need to get the board out when we address all of the
DRC issues, order the parts, and get it off to fab. We actually went down
in component count to ~500 since we removed some "alternate
configuration" stuff in the interest of time and routing. This weeks goals: finish the darn thing, get all of the
parts on order, and most importantly, sleep. Alot. And maye eat, too. 3-18-2007 This week was spent doing layout. Here's what the board
looked like when we started. First are the cad views w/rats nest: starting, progress on 3/12, 3/14.
Here's the 3D views: 3/14 front and back, and 3/18 front
and back. This took about 80 hours and 3
gallons of coffee. I actually ended up buying a larger 20.1"
flat-panel monitor from Dell to make this part easier. The extra
real-estate really helps when laying out something this big. I annotated
the latest front and back pictures so you can see what each
section of the board is used for. These were all taken about 3:00am. Changes since then
include removing some of the headers that were used for configuration and
replacing them with SMT DIP switches. They take up less space and make
routing easier. We now have the bottom layer of the upper part of the board
(where the RF control section is) mostly routed. Still need to do the top
layer and finish routing the power rails. The original design had a board
stack-up of signal-ground-power-signal. We removed the dedicated 3rd layer
power plane and made it a signal layer as well for ease of routing. Plus,
with as many voltage rails as we have, a dedicated power plane doesn't help
all that much. So currently we are dedicating layer 3 for routing power +
signals, and top and bottom layers are signals. Ground plane stays where
it's at. We also spent a few hours this weekend looking for EMI
shields for the board as well. If you look at the top view of the latest drawings, you can see
where we dropped some fat traces for an EMI shield. When we actually choose
the final shield, we'll replace those traces with the shield footprint.
Those traces just serve as a demarcation line so we can get a rough idea of
where we can place components and route signals. So far, the likeliest
vendor is Fotofab. They have some
COTS shields that we can use. Unfortunately, I can't find the exact size we
need, so we might have to go with multiple shields. The drawback from that
is that we'd then have to move some switchers to the back plane due to the
extra space that multiple shields will consume. I'll check at work this
week and see if I can get some of our mechanical guys to craft some custom
shields for me, that's really the optimal solution. If not, then unless we
can find something better, Fotofab will be it for the shields a nd we'll
have to move switchers around. We'll finish routing of the main board this week, probably
by Friday, but this won't include the FPGA. For the FPGA, we can choose
what signals go where, though there are restrictions on some of the IO
banks usage due to the fact that bank 2 has pins that are dual purpose: at
configuration the pins are used to access the flash, and then at
"runtime" they can be reconfigured by the user. However, we don't
want those signals to go to anything critical, like the PC104 bus or the RF
control signals, because at configuration time they'll be out of our
control. So we'll route all of the board up to the FPGA. Based on where the
signals end up, we'll assign them to appropriate FPGA pins. This will allow
us to assign the pins in a manner that will facilitate easy routing,
minimize cross-talk between signals, and group the signals in a logical
manner. The goal then is to have this all finished by Sunday ready for
tape-out. Hopefully we make that, but there's still a lot to do. One other item that we're keeping in our back pocket to put
on the board is some extra RAM. We have some samples of 64MB DDR-133 RAM
from Micron.
It's fast, small (10mmx11mm), lower power RAM designed for mobile
applications. It could be used for buffering large amounts of data, or we
we could could even implement a synthesizable DSP core in the FPGA. This
RAM gives a lot of flexibility if we choose to use it, so we'd like to put
it in if we get time. We'll see where we sit after routing the rest of the
board. If we have time, we'll add the RAM in, if not, we'll leave it out.
Unless, of course, the professor overrides us and says he wants it in :) Goals this week: finish routing, finalize RF/EMI shield
choice. 3-11-2007 Layout is progressing as well as we could hope. Total BOM
part count is 533 right now, but it is going to increase a bit since we
still need to add another switching power supply. We increased the board
size 1.5" in length and .4" in width. The switchers
(buck-regulators) have been moved to the newly created area aft of the
PC104 connector, which not only frees up a lot of space, but also mitigates
noise concerns since the noisy switchers (we're using the LTC3407-2 series
which operates at 2.25 MHz) are moved further away from the critical analog
circuits on the other end of the board. Here's a 3D view of the front and back of the board as it sits today, ~40% complete. We are going to have to add two more switchers. Power
consumption for the IF amps is 6.5V@100mA. The supply voltage we have on
the board is 15V, so that puts Pdiss of the LDO
(low drop-out regulator) at (15-6.5)*100mA=.85 W/LDO. We have 2 LDO's, so total is 1.7 W! Criminy,
the LDO's are dissipating more power than the IF
Amps... Anyhow, the LDO's are in an SOIC, and
they will not be able to handle that much power dissipation. We have
switched the package to DFN which greatly reduces thermal resistance, but
our power requirements are near the specified dissipation limit. The only
thing in our favor is that there is a temperature control system to keep
the board cool. The downside is that we just do not have enough real-estate
on the board to dissipate that heat. To mitigate this concern, we're going
to add in an LM3100
switcher. This switcher is high-efficiency (~95%), but the trade-off is its
low operating frequency, 1 MHz. Lower frequency means larger inductors, 10
mm x 10 mm to be exact. On the software front, the temperature control daemon is
finished. We will test it with the hardware after spring break. Next up is
the position control daemon. We will start writing the software drivers for
the board after we get it back and then start writing the verilog. At this moment, we have not had time to define
the registers that we will expose to the operating systems address space for
programming over the PC104 bus, and we can’t write the drivers until we
know what registers we will need to write to on the FPGA. Did I mention
that we really need about 3 more people for this project yet? Schedule: we had one made, but it got thrown out the window
when the decision was made to change to single-rail. Now we are in
scramble/panic mode trying to get as much done as we possibly can. We hope
to finish layout and routing of the board this coming week. We will send it
to Advanced Circuits for
fabrication where they have a special
right now for three 4-layer boards for $250. They also have a student
special, so we will price both options to see which is best. We will
purchase 2 boards for the radiometers and 1 for us to butcher with
blue-wires :) We're going to use AAPCB for assembly.
They are located in We figure 1 week for fabrication, 1 week for assembly (worst
case), so the boards will be back by the beginning of April. Not much time
to prepare for EDays, but at least we'll have
something to show. Hopefully, we have not made too many mistakes (there are
always mistakes), and we will at least have a functional board that we can
turn on and connect to the TS7300, even if it will not do much. Did we
mention that we wish we had more people? :) This week’s goals: finish layout, order parts, sleep
(haven't done much of that lately). 3-7-2007 Time to get this up to date.. Back in January, we proposed
changing the existing design from a split-rail system to a single rail
design to improve power efficiency and ease routing. From a design
perspective, it was the right thing to do, from a sanity perspective, we
should've kept our mouths shut. This was an incredible amount of work and
required starting over again effectively from scratch. In the short period
of 1.5 months, we added a Xilinx Spartan 3E FPGA, a totally redesigned ADC
front end including a nifty multi-pole low-pass filter and level shifter
with outstanding common-mode rejection to eliminate ground-loops, a greatly
improved and simplified RTD bias circuit, and a 17-page schematic for our
efforts. With a current component count of 533, we've got a lot of work to
do just in layout and routing. We've essentially finished the schematic and started layout
on Saturday. You can find the schematics and a 3D image of the board as it
currently stands on the documentation
page. Due to size concerns (i.e. we may not be able to fit all the
components), we are going to extend the board out past the connector
1.5". We have room on the TS-7300 to accomodate it, and this gives us
a lot more room for placing parts. Currently, the
switcher's are all placed near the FPGA. Those will get moved aft to the
expanded portion of the board, and when we're done with layout, we may add
one more switcher back there to generate the 5V needed to power the board.
This would enable us to power the board off of a single voltage rail (15V),
where currently we need 2: 15V and 5V. We've simulated all of the important circuits, and we'll
post those simulation results soon (when we get time). We've also written
some Verilog for the PC104 bus interface and simulated that as well.
That'll get posted too, again when we get some time. Though fun, this
project has been an incredible amount of effort for just two people, as you
can see here. We really
needed more people for this effort. Still left to do:
finish layout, possibly add another switcher, write a ton of verilog for
the FPGA, and then write the Linux software drivers. 2-27-2007 The new website is up and running. Be sure to check out the
link to the live demo. This site should be getting updated regularly so
check back soon for more updates. 1-10-2007 Engineering Demo for high school students. Setup demo while
Pat explained our future plans for the radiometer control sytem.
Web site contents © Copyright Elliot
Buller 2007, All rights reserved. |
||||||||||||||||||||
|
|
