Objectives

ECE571 is a senior level as well as an entry level graduate course on VLSI design. The purpose of this course is to provide students with opportunities to learn and practice the entire process of VLSI chip design. There is a substantial amount of design work associates with the lectures. Students will go through various design stages from behavioral modeling using Verilog and their simulation environment, to logic and circuit design, and finally to layout and design verification. All the design activities will be carried out on HP workstations. Up to 5 design labs are scheduled concurrent with the lectures, students are required to submit a design report and to participate in design reviews.
 

IEEE SSCS - Denver Chapter Talks:

Last Updated:

January 17, 2012 3:06 PM