Instructions for Extracting Parasitics for your Layout using xCalibre Tool.

1. Goto to the folder where your layout is stored and create two new files called xcal_tsmc018.rules and run.script. Copy the contents of the example rule file into this newly created xcal_tsmc018.rules file and the example run.script file into the newly created run.script file. You would have to do this for every layout for which you want to extract the parasitics (important).

2. Modify the rule file with your actual layout name, in all places where it says YOUR_LAYOUT.

3. Open your Layout in IC Station & from the main menu goto Translate --> Write GDSII file. In the pop-up window for Output GDSII file type layout_name.gds. Click OK. This will create a gds file for your layout.

4. Now from the main menu, select Calibre --> Run PEX. In the new window, click on Rules. Then browse to find the xcal_tsmc018.rules file. Select the rule file & then click on Load. In the PEX run directory, type in your present working directory. Now click on Output. In the Output section, make sure that the Extraction type is set to Transistor Level & RCC. Also the Netlist Format is set Eldo and Use name from is set to Layout. Now click on Run Control. Set 64 bit version of Calibre PEX and keep the remaining cleared.

5. Now Click on Run PEX. This process will generate _xcal_tsmc018.rules_ file. Close Calibre PEX window, close IC station. Goto to unix prompt and do file search (% ls) to see whether this file has been create or not. If its created, then you are all set to proceed ahead.

6. Now type chmod 755 *.* to grant required permissions.

7. Then type run.script. This will run the run script which contains calibre commands. It will produce netlist which is in Eldo format. We need to modify this netlist to a format which Eldo can understand.

8. Example: (1) Inverter.pex.netlist.

Netlist for an Inverter, produced by Calibre PEX:

* File: inverter.pex.netlist
* Created: Tue Feb 17 10:13:37 2004
* Program "Calibre xRC"
* Version "v9.3_6.5"
*
.include "inverter.pex.netlist.pex"
.subckt INVERTER GND VDD OUT IN
*
* VDD VDD
* GND GND
* OUT OUT
* IN IN
mM0 N_OUT_M0_d N_IN_M0_g N_VDD_M0_s N_VDD_M0_b P L=1.8e-07 W=1.06e-06
mM1 N_OUT_M1_d N_IN_M1_g N_GND_M1_s N_GND_M1_b N L=1.8e-07 W=3e-07
*
.include inverter.pex.netlist.INVERTER.pxi
*
.ends
*
*
Modified Neltist for an Inverter.... Save the modified file as "layout.cir" (You need to do these modifications manually)

.LIB /class/EE571/models/log018.eldo53 TT
v0 GND 0 DC 0
vdd VDD GND DC 1.8V
v1 IN GND pwl(0 1.8 5n 1.8 5.01n 0 5.5n 0 5.51n 1.8 12.0n 1.8)
.tran 0.001ns 30ns 0 0.01ns
.plot v(IN) v(OUT)

mM0 OUT IN VDD VDD pch.6 L=1.8e-07 W=1.06e-06
mM1 OUT IN GND GND nch.12 L=1.8e-07 W=3e-07
*
.include inverter.pex.netlist.INVERTER.pxi
*
.END

Example (2): Inverter.pex.netlist.INVERTER.pxi

File produced by Calibre PEX

* File: inverter.pex.netlist.INVERTER.pxi
* Created: Tue Feb 17 10:13:37 2004
*
x_PM_INVERTER_IN IN N_IN_M0_g N_IN_M1_g PM_INVERTER_IN
x_PM_INVERTER_OUT N_OUT_M1_d N_OUT_M0_d OUT N_OUT_c_5_n PM_INVERTER_OUT
x_PM_INVERTER_GND N_GND_M1_b N_GND_M1_s GND PM_INVERTER_GND
x_PM_INVERTER_VDD N_VDD_M0_b VDD N_VDD_M0_s PM_INVERTER_VDD
cc_1 N_OUT_M1_d N_IN_M1_g 33.8293f
cc_2 N_GND_M1_s N_OUT_c_5_n 7.0774f
cc_3 N_GND_M1_s N_OUT_M1_d 44.4543f
cc_4 N_GND_M1_s N_IN_M1_g 5.91481f
cc_5 N_VDD_M0_s N_GND_M1_s 7.38238f
cc_6 N_VDD_M0_s N_OUT_M1_d 60.4408f
cc_7 N_VDD_M0_b N_OUT_M0_d 21.2979f
cc_8 N_VDD_M0_s IN 15.0894f

Modified file (You need to do this manually)

* File: inverter.pex.netlist.INVERTER.pxi
* Created: Tue Feb 17 10:13:37 2004
*

cc_1 OUT IN 33.8293f
cc_2 GND OUT 7.0774f
cc_3 GND OUT 44.4543f
cc_4 GND IN 5.91481f
cc_5 VDD GND 7.38238f
cc_6 VDD OUT 60.4408f
cc_7 VDD OUT 21.2979f
cc_8 VDD IN 15.0894f

9. Remember, to save the "inverter.netlist.pex" file as just inverter.cir. Now run it in ESIM, just the same way you did it for your schematic netlist. The simulation results may not be the same as that obtained from schmetatic netlist. Now change your W & L values in Layout netlist to get equal rise & fall times. Once you know these W & L values, then go ahead & change them in your layout. Donot forget to change them in your layout, since you would be using you layouts in next lab...

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If your circuit is not working properly, after all possible logic checks, then there can be a layout error - a short between nets. Use the following few lines to fix it.

While doing a parasitic exraction it is possible that there are more than one net short,
the way to find this out is to check the transcript that is created bt the run_script file.

use the command "run_script > transcript" to create the transcript.
use "vi transcript" to view it, check if any short circuit information is present.

If you find any short circuts listed, then use/add the following command line in your rules file

" LVS ISOLATE SHORTS YES BY LAYER UNMERGED CELL ALL "

After this do the extraction. Then you can do a LVS from the Calibre menu in IC to do a check.
Compare the Layout to netlist, the layout is the GDS file and the netlist will be the one that was
created by PEX. In LVS you can see a SHORTS Database. View it and highlight the shorts one after the other.

Now you know where the short is, fix it and be happy.

[Written by: Charles Thangaraj]
[August 9th 2004 - Latest Update]

For a full description and more information please click here.

[Previous Update: 17th Feb 2004 by Chinmay Gupte.]