Lab Content

Lab 1: Layout and simulation of basic CMOS gates

Lab 2: Layout and simulation of Transistor Level master-slave DFF

Lab 3: Layout and simulation of 3-bit up-down counter

Lab 4: Capture and simulation of a bit-slice adder in static, dynamic, and PTL

Lab 5: Capture and simulation of a 16-bit bit-slice adder in static, dynamic, and PTL

Lab 6: Power consumption analysis of the 16-bit adder in static, dynamic, and PTL

Lab 7: Static and dynamic timing analysis of the 16-bit adder in static, dynamic, and PTL

Documents necessary for completing the lab exercises.

ELDO Spice Tutorial     (Device table)    

User Manuals, tutorials and references

New enviroment setup tutorial by Joe (Spring 07)

IC_Station quick tutorial for DRC and Xcalibre by Joe

ELDO Users Manual

IC Station Users Manual

Calibre Users Manual

Sample Netlist File

Introduction to Mentor Graphics

Tutorial For Running Calibre Parasitic Extraction {Latest Update 01/11/2005}

Epic Tools Tutorial [Boring HTML Version] {Old outdated - for transition purposes}

Epic Tools Tutorial [Snazy PDF Version] {Latest 01/11/2005}

In order to receive credits for the Lab section, each lab needs to be checked off during the week that lab is scheduled. A brief lab report is due the following week. The lab report must contain:

• a list of items completed
• a list of items not completed (if any)
• schematic and VHDL models
• simulation results
• analyses and explanations