VLSI System Design (EE575)
Labs 6 and 7
 
Power and Timing Evaluations of Static Logic, Dynamic Logic, and Pass Transistor Logic Circuits

 

1. Objectives

The objective of this lab is to further evaluate the performance and the power requirements of static logic, dynamic logic, and pass transistor logic circuits. You will use the adder slice that you have developed in Lab4 to build a more complex adder. The performance and the power requirements will be evaluated using pathmill and nanosim.

2. Lab Description and SpecsFunction:

Use the 16-bit adder developed in Lab 5.

Inputs:

A[0:15], B[0:15]: 16-bit adder data input signals,

Cin: 16-bit adder carry input,

Clk, Clkbar: clock signal and its complement.

 

 Outputs: S[0:15]: 16-bit adder sum output,

Cout: 16-bit adder carry output.

Deliverables: Important, interesting, or relevant outputs from the pathmill and nanosim. (Do not show all output)Analyze both the outputs. How do they compare to SPICE?Answer questions like: What is the point of these tools?
Why are they valuable?
With the information from these tools, how can you improve your design?

3. Recommended Procedures

The following lists the recommended steps:
  1. You must type this in your terminal before running any epic tool:
    source /mentor/csu_setup/epic_setup.csu
  2. Extract the esim netlist and the parasitic RC from the 16-bit adder layout,
  3. Copy the converter_netlist.pl in a separate file and save it with this name in your current working directory. At the unix prompt, type chmod 755 converter_netlist.pl and then converter_netlist.pl. Enter your design.cir filename. The perl script would output two separate netlists (design_pathmill.spi and design_nanosim.spi). Use the first one with pathmill whereas the second one with nanosim. By running the perl script, you are basically converting "*.cir" netlist into "*.spi" format. NOTE: The perl script will only work, if you have named your signals as A_0, B_10, Sum_12 and so on. Otherwise you need to convert the input signal names manually from whatever you may have named to A[0], B[10] , Sum[12] and so on.
  4. Run pathmill to determine its performance limitation.
  5. Use a set of functional vectors (refer to vector file example) to run nanosim to determine its power consumption requirement.