1. Objectives
2. Lab Description and Specs
Function:
Inputs:
Cin: Adder carry input,
Clk, Clkbar: clock signal and its complement.
Cout: Adder carry output.
Same as Lab 4 except Power vs. Delay curves.
NEW...
1) Static & PTL Circuit: (a) Propagation delay between B0 and C16 (Use test case FFFF + 0000 + 0 = FFFF followed by test case FFFF + 0001 + 0 = 10000) (b) Max Freq of operation (same test case as (a)). Here increase the freq of B0 until either of all Sum or C16 is invalid) (c) Functionality (use test cases FFFF + 0000 + 1 and 2222 + 1111 + 1)
2) Dynamic Circuit: (a) Propagation delay between CLK(+ve edge) and C16 (use the same test case that you used for static circuit) (b) For setup/hold time use the same test case that you used in (a) and measure the setup/hold time for the input B0. (c) Max freq measurement same as static/ptl. (d) Functionality same as static/ptl.
Include all three netlists and plots (showing measurements with cursor) for all cases with all conditions (violating and non-violating). Plots must be clear and readable!!!! Show calculations at the bottom of each plot.