VLSI System Design (EE575)
Lab 3
 
A Three-Bit Up-Down Counter

 

1. Objectives

The objective of this lab is to design a synchronous circuit and determine its timing characteristics, i.e. setup time, hold time, and the maximum operating frequency. You will also learn the differences in performance using different layout styles.

2. Lab Description and Specs

Function:

Three-bit up-down counter using master-slave D-FFs with a clear signal.Inputs: Clr: Counter clear signal,

Up/Down: Up/Down count control,

Clk1: phase-1 non-overlapping clock,

Clk2: phase-2 non-overlapping clock.

Outputs: Q0-Q2: Output of the counter.Deliverables:Schematic from DA of 3-bit up-down counter with clear.
Clean netlist from schematic.
Output waveforms from schematic simulation showing:
proper up and down counting and clear functionality running at a low frequency,
setup and hold time measurements,
proper up and down counting and clear functionality running at max. frequency. Layout from IC of 3-bit up-down counter with clear.
Clean netlist from schematic.
Output waveforms from layout simulation showing:
proper up and down counting and clear functionality running at a low frequency,
setup and hold time measurements,
proper up and down counting and clear functionality running at max. frequency.Compare the setup and hold times and maximum operating frequency from schematic and layout. Explain any difference.3. Recommended Procedures For this lab you can use the basic CMOS gates (INV/NAND/NOR) created in Lab1 and the D-FF created in Lab2. The following lists the recommended steps:
  1. Generate transistor level schematic in DA.
  2. Verify schemic by simulating extracted netlist in Esim.You might want to use a bus. See the eldo manual.
  3. Generate layout in ICstation based on schematic.
  4. Run DRC and ERC.
  5. Verify layout in Esim with extracted netlist.