VLSI System Design (EE575)
Lab 2
 
Transistor-Level Master-Slave D-FF

 

 

1. Objectives

The objective of this lab is to design a D-FF in VLSI. The D-FF’s timing characteristics, i.e. the setup time and hold time, need to be determined for the given design. You will also learn how to implement weak feedback in storage elements.

2. Lab Description and Specs

Function:

D-FF with a master and a slave stage each of which is activated by a phase of non-overlapping clock signal. Use a weak inverter in the feedback loop within each stage rather than using an equal strength inverter with a switch. Inputs: D: D-FF data input,

Clk1: phase-1 non-overlapping clock,

Clk2: phase-2 non-overlapping clock.

Outputs: Q: Output of the D-FF.Deliverables: Schematic from DA for your final D-FF design showing proper sizing, valid instance names, and correct model properties.
Clean netlist from schematic
Output waveforms of schematic simulation showing:
proper D-FF operation, setup time measurement, hold time measurement, delay measurement.Layout from IC for you final D-FF design
Clean extracted netlist from layout.
Output waveforms of layout simulation showing:
proper D-FF operation, setup time measurement, hold time measurement, delay measurement.Explain your overall workflow from start to finish.
What is the sizing ratio of your weak inverter? Why is it this (hint: use a Vout vs. Vin graph, reference your Vth investigation from Lab 1)?
How does changing Ln/Lp affect the performance metrics of your D-FF?
Compare the setup, hold, and delay times from schematic to layout. Explain any difference.
3. Recommended Procedures For this lab you can use the inverters created in Lab1. Use the inverter with balanced output as the strong inverter and an inverter with Ln/Lp ratio greater than 3 as the weak inverter. Use n-channel MOS transistors as switches. The following lists the recommended steps:
  1. Create a transistor-level schematic in DA and adjust the transistor sizes to balance the output.
  2. Extract a netlist from your schematic.
  3. Simulate it in Esim and measure the setup time (can be negative), the hold time (can be negative) and the maximum delay.
  4. Reduce the Ln/Lp ratio of the feedback inverter to observe its impact on overall FF performance.
  5. Use ICstation to assemble the D-FF layout using transistor sizes obtained from DA schematic.
  6. Run DRC and ERC checks for the generated layout,
  7. Extract a netlist from your layout,
  8. Run Esim to verify the functionality of the layout.