EE 550             Spring 2006

PRESENTATIONS

Topic:
A requirement of EE 550 is a presentation covering a topic closely related to the course. A set of papers are given below on which you may base your presentation. Please use the listed paper(s) as the starting point for your preparation, but use other related works to enhance the presentation.
A topic not in the list  may be allowed with prior approval of the instructor. The topic should not be related to a presentation or a paper that you have done as a part of another course. 

General Information:
E-mail  your presentation title  and a short summary (less than half a page) for approval to Anura.Jayasumana@colostate.edu as early as possible, but not later than March 27.  Include the dates you prefer for your presentation, as well as the names of your red team partners (see below). To avoid multiple presentations on the same topic and time conflicts,  topics and time slots   will be allocated on a first-requested  first-served basis.

A presentation is expected to be 35 minutes long. The lecture slots  on 3/30, 4/4, 4/6, 4/11, 4/13, 4/18, 4/20, 5/2    are available for presentations.
We will also hold two additional lectures on 4/6 and 4/11 from 3:30-5:00 that will be available for presentations (we will not meet on 4/25 and 4/27).
Up to 2 presentations that  cannot be scheduled during these times will be held outside class hours or during the finals week at a  mutually agreeable time.

The slides have to be your own creations. You may use figures, tables etc from other sources, provided those are identified by the appropriate reference immediately following the figure/table.
Include a list of all the references you've relied on for the presentation. 
E-mail your slides (ppt) to the instructor two working days prior to the presentation. Instructor will make copies for distribution.

Practice Session

Making effective presentations is an integral part of any career. Giving presentations in a class makes you learn the material well, and provide a good venue to practice your presentation skills.
A good presentation will require thorough preparation.  Others are going to spend time listening to you, therefore it is essential that you make a sincere effort to make it a fruitful experience for everyone involved. Identify the problem, concepts, results, possible extensions, and most importantly provide  your opinion of the work.

Form a team of two to three (Red Team) so that team members can critique each others presentations prior to the class presentation.
The Red Team should meet at least three working days prior to the class presentation, listen to the presentation  and help fine-tune the presentation. 

Grading

Presenter:                                               
Technical  Depth            5                       
Clarity of presentation     5
Understanding/ Q&A      5
Time Utilization             5
Slides                            5
(Red-team feedback should help in areas of  clarity, time utilization, and slides)

Red-Team Members:
Will receive credit for class participation  based on overall quality of the presentations they have contributed to.



  
  Date  
Presenter
 Red Team

Microprocessors



Sun's big splash [Niagara microprocessor chip]; Geppert, L.; IEEE Spectrum, 42:1;  Jan. 2005 pp.  56 – 60
Niagara: a 32-way multithreaded Sparc processor; Kongetira, P.; Aingaran, K.; Olukotun, K.;  IEEE Micro    25:2; 2005   pp.    21- 29 

01377878.pdf
01453485.pdf 		4/4 Bharat Viswamani A. Jayaseelan
R. Sivakumar
P. Manja

IBM Power5 chip: a dual-core multithreaded processor; Kalla, R.; Balaram Sinharoy; Tendler, J.M.; IEEE Micro   24:2;  2004  pp.    40- 47

 01289290.pdf 4/20
Tejkiran Balijepalli
 G. Bhatia
A. Karegar
M. Koshy
Introducing the IA-64 architecture; Huck, J.; Morris, D.; Ross, J.; Knies, A.; Mulder, H.; Zahir, R.; IEEE Micro  2000  20:5; pp.   12-23
Itanium processor microarchitecture; Sharangpani, H.; Arora, H.; IEEE Micro    20:5;  2000 pp.   24-43 		00877947.pdf

00877948.pdf


Itanium 2 processor microarchitecture;  McNairy, C.; Soltis, D. pp. 44- 55

Montecito: a dual-core, dual-thread Itanium processor; McNairy, C.; Bhatia, R.; IEEE Micro    25:2; 2005 pp.    10- 20

 01196114.pdf
01453484.pdf		 4/13
 Jennifer Flint H. Dittmer
A. Horiuchi
K. Williams
S. Oliver

The GeForce 6800;  Montrym, J.; Moreton, H.;  IEEE Micro    25:2 2005; pp.    41- 51

01453487.pdf 4/11**
4:15PM
 Kirk Williams
 S. Oliver
J. Flint

High-performance throughput computing; Chaudhry, S.; Caprioli, P.; Yip, S.; Tremblay, M.;   IEEE Micro  2005  25:3; pp.    32- 45

 01463182.pdf


Kilo-instruction processors: overcoming the memory wall;  Cristal, A.; Santana, O.J.; Cazorla, F.; Galluzzi, M.; Ramirez, T.; Pericas, M.; Valero, M.; pp.    48- 57

 01463185.pdf 4/6**
4:15PM
 Robert
Salyer
 C. Riley
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs;
Taylor, M.B.; Kim, J.; Miller, J.; Wentzlaff, D.; Ghodrat, F.; Greenwald, B.; Hoffman, H.; Johnson, P.; Jae-Wook Lee; Lee, W.; Ma, A.; Saraf, A.; Seneski, M.; Shnidman, N.; Strumpen, V.; Frank, M.; Amarasinghe, S.; Agarwal, A.;   Micro, IEEE		 00997877.pdf


MP3 optimization exploiting processor architecture and using better algorithms; Anguita, M.; Martinez-Lechado, J.M.; IEEE Micro  2005  25:3; pp.    81- 92

 01463188.pdf


Configurable processors: a new era in chip design; Leibson, S.; Kim, J.; Computer, 38:7,  July 2005; pp.  51 - 59
01463107.pdf 4/4
 Arun Jayaseelan
 B. Viswamani
P. Manja
R. Sivakumar

Performance



An Experimental Study of Soft Errors in Microprocessors;  Saggese, G.P.; Wang, N.J.; Kalbarczyk, Z.T.; Patel, S.J.; Iyer, R.K.;  IEEE Micro 2005   25:6;  pp.    30- 39

 01566554.pdf 3/30
Henry Dittmer
 A. Horiuchi
J. Flint

Pentium 4 performance-monitoring features;  Sprunt, B.;  IEEE Micro  2002  2:4; pp.    72- 82

 01028478.pdf 4/6**
3:30PM
 Patrick Moranville K. Knapp

The basics of performance-monitoring hardware; Sprunt, B. IEEE Micro  2002  2:4;
pp.    64- 71

 01028477.pdf 4/13
 Michael Steigerwald
 M. Koshy
A. Karegar

Evaluating InfiniBand performance with PCI Express; Jiuxing Liu; Mamidala, A.; Vishnu, V.; Panda, D.K.; IEEE Micro  2005  25:1; pp.    20- 29

 01411713.pdf 4/11
 Manoj Koshy
 A. Karegar

Memory Systems



Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1; Suh, T.; Lee, H.-H.S.; Blough, D.M.; IEEE Micro  2004  24:4;  pp.    33- 41

 01331277.pdf


Itanium 2 processor 6M: higher frequency and larger L3 cache;  Rusu, S.; Muljono, H.; Cherkauer, B.; IEEE Micro  2004  24:2; pp.    10- 18

 01289279.pdf 4/6
 Aron Horiuchi
 H. Dittmer
J. Flint

Virtual memory in contemporary microprocessors; Jacob, B.; Mudge, T.; IEEE Micro  1998 18:4 pp.   60-75

00710872.pdf 3/30
 Puneet Prakash

Virtual-address caches. Part 1: problems and solutions in uniprocessors; Cekleov, M.; Dubois, M.;  IEEE Micro 1997 17:5;  pp.   64-71;

Virtual-address caches. Part 2: Multiprocessor issues; Cekleov, M.; Dubois, M.; IEEE Micro  1997 17:6;  pp.   69-74 		00621215.pdf
00641599.pdf


Two fast and high-associativity cache schemes;  Chenxi Zhang; Xiaodong Zhang; Yong Yan; IEEE Micro 1997 17:5; pp.   40-49

 00621212.pdf


Input/Output



The Memory Stick; Araki, S.;  IEEE Micro  2000  20:4;  pp.   40-46

 00865865.pdf 5/2
 Chris Riley
  

InfiniBridge: an InfiniBand channel adapter with integrated switch; Eddington, C.R.;  IEEE Micro  2002  22:2; pp.    48- 56

 00997879.pdf 4/11**
3:30PM
 Keith Knapp

Hardware/software cost analysis of interrupt processing strategies; Samadzadeh, M.H.; Garalnabi, L.E.; IEEE Micro  2001  21:3; pp.   69-76

 00928766.pdf

                   

An empirical analysis of the IEEE-1394 serial bus protocol;  Steinberg, D.; Birk, Y.; IEEE Micro  2000  20:1; pp.   58-65

 00820054.pdf 4/11
 Anita Karegar
USB Interface    
usb20g.pdf
 4/20
 Scott Oliver
 J. Flint
K. Williams

Architectural Features



Superscalar instruction issue;  Sima, D.;      pp.   28-39

 00621211.pdf


Exploiting Instruction and Data-Level Parallelism;  Roger Espasa, Mateo Valero; IEEE Micro 1997 17:
00621210.pdf


The design space of register renaming techniques; Sima, D.;  IEEE Micro  2000  20:5; pp.   70-83 00877952.pdf


General Topics



The challenges of wearable computing: Part 1;  Starner, T.; pp.   44-52
The challenges of wearable computing: Part 2; Starner, T.;  pp.   54-67; IEEE Micro 		00946681.pdf
00946683.pdf		 4/6
 Ramnathan Sivakumar
 A. Jayaseelan
B. Viswamani
P. Manja

Toward quantum computation: a five-qubit quantum processor; Steffen, M.; Lieven, M.K.; Vandersypen; Chuang, I.L.; IEEE Micro  2001  21:2;  pp.   24-34

 00918000.pdf 4/18
 Prasanna Manja
 A. Jayaseelan
B. Viswamani
R. Sivakumar

IBM's Deep Blue Chess grandmaster chips;  Feng-Hsiung Hsu; IEEE Micro  1999  19:4; pp.   70-81

 00755469.pdf 4/18
 Gautam Bhatia
Making computers invisible; Sakamura, K.; IEEE Micro  2002  22:6; pp.    7- 11 01134335.pdf
Not Available

High performance RISC microprocessors; Choquette, J.; Gupta, M.; McCarthy, D.; Veenstra, J.; IEEE Micro  1999  19:4; pp.   48-55

 00782567.pdf
Not Available
Deep submicron microprocessor design issues; Flynn, M.J.; Hung, P.; Rudd, K.W.; IEEE Micro  1999  19:4;  pp.   11-22
Design challenges of technology scaling; Borkar, S.; IEEE Micro  1999  19:4; pp.   23-29 		00782563.pdf
00782564.pdf
Not Available

Microprocessor design issues: thoughts on the road ahead; Flynn, M.J.; Hung, P., Pp.    16- 31, IEEE Micro  2005  25:3
Computer architecture: challenges and opportunities for the next decade; Agerwala, T.; Chatterjee, S.;  IEEE Micro  2005  25:3;  pp. 58- 69
01463181.pdf
01463186.pdf

Not Available
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