1. Getting Started
The following links to documents and web link(s) provide procedures to get you started. Specifically, going from a Windows Operating
System (OS) to a UNIX OS is addressed. A basic knowledge of Unix will be required in the class.
2. Verilog and Very high speed integrated circuit Hardware Description Language (VHDL)
A very important concept for a Hardware Description Language (HDL)
programmer to understand is to distinguish the difference between
HDL code that is executed concurrently and HDL code that is executed
sequentially.
For VHDL, any code within an ARCHITECTURE block is executed
concurrently based on "events" that affect the code, such as changing
input values. So, ordering with an ARCHITECTURE block is irrelevant.
However, PROCESS blocks are slightly different. PROCESS block execution
is "scheduled" based on triggering "events". This implies that a PROCESS
block will start executing when changes in its "sensitivity list" are
detected.
For variables, which exist inside a PROCESS block, the assignment to
the variables happens as soon as the assignment operator ( ":=" ) is executed.
For signals, the assignment is "scheduled" when the assignment operator ( "<=" )
is executed, and all assignments will occur when the PROCESS completes.
Therefore, variables behave just like C or C++ variables. signals will
still execute sequentially (the last assignment 'wins'), but their value
will not change until it is "scheduled".
The following link illustrates this
concept. VHDL code and the simulated results are provided.
Verilog works similiarily, with two different kinds of assignment: blocking
and non-blocking. Refer to a Verilog text for more detail.
The following documents provide a Verilog and VHDL quick reference quides of the syntax:
Verilog |
Verilog quick reference quide of syntax. |
VHDL |
VHDL quick reference quide of syntax. |
IEEE 1164 Package |
Provides the IEEE 1164 library package. This is a quick reference guide. |
3. Mentor Graphics ModelSim
Mentor Graphics ModelSim is the Electronic Design Automation (EDA) tool that permits you to simulate your Verilog
or VHDL design prior to going through the steps to implement your design in an FPGA. In addition,
information is provided, if you elect, to download a free version of Mentor Graphics ModelSim.
(However, this does not obviate your requirement to attend lab.)
Introduction Information (This is all you really need to know):
Detailed Information:
ModelSim Tutorial v5.7 |
Provides a tutorial using ModelSim v5.7. |
ModelSim User's Guide |
Provides the ModelSim User's Guide Manual. |
To Download ModelSim |
Provides the link where you can download a free Xilinx "student edition" version of Mentor Graphics ModelSim. This will allow you to compile and run your verilog on your own PC. However,
you must sign-up and register for the software. The version being downloaded may be a different version than
what is used in lab. |
4. XESS Corporation Field Programmable Gate Array (FPGA) Protoboard
The following links to documents, web links and web pages provide you an introduction to the XESS Corporation Field
Programmable Gate Array (FPGA) prototying board, the XSA-50. The FPGA protoboard permits you to verify on hardware
your Verilog or VHDL model of your circuit design.
The XSA-50 protoboard uses the Xilinx Spartan II FPGA with a maximum 100MHz clock frequency that provides you a
capacity of 50,000 gates to implement your logic in hardware from your Verilog or VHDL code.
The XSA-50 protoboard is attached to an extension board, the XSTend board, to provide additional functionality.
Also included in this section is additional detailed information on the XESS protoboards.
Introduction Information (This is all you really need to know):
Design Flow |
Provides the "big picture" in going from a VHDL code representation of your design to implementing the design in
hardware on the protoboard. |
Protoboard Overview |
Provides an overview of the XSA-50 & XSTend board functionality. |
I/O Pin Mappings |
Provides the pin mappings for Input/Output to/from the FGPA. Input Devices: Dip Switches, Switches & Parallel Port "DIP Switch"
Output: Bargraph LEDs & 7-Segment Displays. |
Clocking on the protoboard |
Provides different procedures to implement clocking requirements such as finite state machines on the XESS Protoboard. |
GSXTOOLS |
Provides procedures on using utilties provided by XESS to: test the protoboard, download your design to the protoboard,
using the parallel port "DIP Switch" & modifying the programmable clock. |
Lessons Learned |
Provides XESS protoboard design features. |
Detailed Information:
XSA-50 |
Provides the detailed information on the XSA-50 protoboard, including other ports, jumper settings, schematics and pin specific
functionality. |
XSTend |
Provides the detailed information on the XSTend board, including additional ports/peripherals, jumper settings, prototyping area and header,
schematics and pin specific functionality. |
AK4520a |
Provides the data sheet on the 20-bit stereo chip used on the XSTend protoboard. |
GSXtools |
Provides the user's manual on using utilties provided by XESS to: test the protoboard, download your design to the protoboard,
using the parallel port "DIP Switch" & modifying the programmable clock (This is an older version of the current tools, but the
most current manual). |
ISE 4.1 |
Provides a tutorial using the Xilinx ISE 4.1 EDA Tool and the XSA-50 from the XSA-50 perspective. (This is an older
software version, but the concepts remain the same). |
XESS Corp. Website |
Provides numerous FPGA examples (especially with other peripheral devices), documentation and other resources. |
5. Xilinx Spartan II and ISE 5.x
The Xilinx Spartan II is the FPGA used on the XESS FPGA protoboard to verify your design from Verilog or VHDL in hardware.
The documents provided below provide you an overview of the Spartan II, as well as detailed specifications.
The Integrated Software Environment (ISE) 5.x (Project Navigator) is Xilinx's design flow program that permits you to synthesize your design, map, place and route your design onto the
Spartan II FPGA, as well as, generate the bit file to be downloaded into the XESS protoboard (as illustrated
here). In addition,
information is provided, if you elect, to download a free version of the Xilinx design flow program (ISE 5.x).
(However, this does not obviate your requirement to attend lab.)
Introduction Information (This is all you really need to know):
Project Navigator |
Provides a reference guide to synthesize, route, place and map your design onto the XESS XSA-50 FPGA protoboard, as well as, generate the bit stream and downloading your design onto the protoboard. |
Detailed Information:
PLD Overview |
Provides an introduction and overview of Xilinx Programmable Logic Devices. |
PLD Technical Overview |
Provides a technical overview of Xilinx FPGAs for the first-time user. |
Spartan II Overview |
Provides an overview of the Spartan II FPGA. This includes the internal organization of the FPGA. |
Spartan II Introduction |
Provides an introduction to the Spartan II family of FPGAs. |
Spartan II Functional Description |
Provides the detailed functional description of the internal organization of the Spartan II FPGA. |
Spartan II Pinout |
Provides a pinout chart of the Sparatan II chip signals and description of the functions. |
ISE 5.x |
Provides a detailed tutorial using the Xilinx ISE 5.x EDA Tool from the Xilinx FPGA perspective. |
Using Webpack & ModelSim |
Provides an introduction to using Xilinx Webpack & Mentor Graphics ModelSim EDA tools. |
To download Project Navigator |
Provides the link where you can download a "student version" of Xilinx Project Navigator. Project Navigator is the application
package associated with ISE5.x Webpack. However,
you must sign-up and register for the software. The version being downloaded may be a different version than
what is used in lab. |
6. Mentor Graphics Design Architect (DA)
Mentor Graphics DA is an EDA tool that permits you to develop a schematic representation of your design.
Introduction Information (This is all you really need to know):
DA Quick Reference Guide |
Provides the a list of most common features used in DA to build a schematic capture of your circuit. |
About Force Files |
Provides typical commands that can be used to generate a force file for simulating a circuit representation or Verilog/VHDL representation of design. |
Detailed Information:
7. Mentor Graphics QuickSim II
Mentor Graphics QuickSim is an EDA tool that permits you to simulate your schematic representation that was built using DA.
Introduction Information (This is all you really need to know):
QuickSim Quick Reference Guide |
Provides a condensed version of the manuals to simulate your design. |
About Force Files |
Provides typical commands that can be used to generate a force file for simulating a circuit representation or Verilog/VHDL representation of design. |
Detailed Information:
8. Additional Links That Might Be Helpful
Created by: David M. Sendek and Stacey Secatch, July 2003
Updated: January 2004