1. LEDs & 7-Segment Displays

LEDs and 7-Segment Display segments will be illuminated after you download your design for output pins that you did NOT define. This is normal. Just pay attention to the output LEDs where you mapped your outputs.


2. Push-button SW2 (on XSA board) & S2 (on XSTend board)

Do NOT depress push-button SW2 on the XSA-50 or the XSTend board. This action erases the FPGA and your downloaded design will not work. For the use of this push-button switch, refer to the XSA & XSTend User's Manuals.


3. GXSport Utility & 7-Segment Displays

Do NOT toggle pin 7 of the software parallel port input when outputs are mapped to a 7-Segment display. This will in effect reset the FPGA and your downloaded design will not work.


4. Programming the FPGA

One of the features that XESS Corporation provides in the XSA-50 protoboard is a way to tell if the download and programming of the FPGA was satisfactorly. If the right most "dot", "point" or "decimal point" of the 7-segment display on the XSA-50 board is illuminated after a download, then the protoboard received a valid configuration bitstream.


5. Combinational Logic

It is best to use an "if...elsif...else" construct or "case" statement to cover all combinations of comparison logic. Otherwise, the Xilinx Project Navigator synthesizer will not "know" if all possible cases were covered and it may yield unexpected results.


6. DS1075 Programmable Clock on the XSA-50 Protoboard

Even though the DS1075 programmable clock is rated to accomodate 100MHz, The XESS XSA-50 protoboard has set the default (clocking) divisor to be 2. In other words, the FPGA is clocked at 50MHz. Consequently, if a user is using the programmable features of the DS1075 programmable clock via the GXSSETCLK utility, to restore the XSA-50 protoboard to it's default clocking configuration, one must restore the default divisor using the GXSSETCLK utility to 2. This will store 2 as the divisor in the DS1075 programmable clock's EEPROM.


7. External Clocking

If a user opts to use external clocking to the FPGA on the XESS XSA-50 protoboard, the maximum external clock that can be used is 25MHz. To use external clocking, the "External Clock" feature is selected in the GXSSETCLK utility and the divisor can be in the range of 1 to 2052. After using external clocking on your design, remember to reset the DS1075 programmable clock to it's default clocking configuration as discussed above.


8. GXSTEST Utility

If a clocking divisor is set higher than 4 (as discussed above), the GXSTEST will fail. This is because the Delay Lock Loops (DLLs) in the test circuit will not lock if the clock is less than 25MHz.


9. XSA-50 & XSTend board Power Supply

The source of power is through a 9VDC 500mA class 2 power supply (or an ATX power supply). Power can be applied to either the XSA-50 or the XStend board, but NOT both. Either power supply source can power both boards, but only 1 source is required. However, in the Digital Design Lab, a lower rated (in terms of AMPS) power supply may be in use. This should work for all designs being accomplished in EE451. If your design is complicated and/or you are using other peripheral devices, you may require the 9VDC 500mA class 2 power supply (or ATX power supply).