Lab Schedule ECE 450

WEEK	Lab Content	Duration	Date from - Date to
2-3	Lab 1: Design of a 3-bit ALU (Manual Design)	2-week lab	8/28 - 9/8
4	Lab 2: Design of a 3-bit ALU (Verilog)	1-week lab	9/11 - 9/15
5-6	Lab 3: Design of a Subway Control Logic (manual schematic)	2-week lab	9/18 - 9/29
7	Lab 4: Design of a Logarithmic Multiplier (Verilog)	1-week lab	10/2 - 10/6
8-9	Lab 5: Design of a Logarithmic Multiplier (Manual schematic)	2-week lab	10/9 - 10/20
10	Lab 6: Design of a Gray Scale Counter (manual schematic)	1-week lab	10/23 - 10/27
11	Lab 7: Design of a Pulse Clock Generator and a Pyramid Counter (Verilog)	1-week lab	10/30 - 11/3
12-13	Lab 8: Subway Signal Control Logic (manual schematic & Verilog)	2-week lab	11/6 - 11/17
14-15	Lab 9: Design of a Complex Finite State Machine	2-week lab	11/27 - 12/8

In order to receive credit for the lab section, the pre-work is to be completed prior to commencement of lab and that each Verilog related lab needs to be demonstrated to the TA during the week the lab is scheduled. A lab report is due at the end of each lab before starting the next lab.
Here is more detail regarding lab grading: 450 Lab Expectations
Here to download Cadence Virtuoso installation package: Cadence Virtuoso