Field Programmable Gate Array (FPGA) Design Flow
The illustration on this webpage provides the methodology that one will follow to use Verilog or Very high speed integrated circuit Hardware Description Language (VHDL) to implement a design onto the XESS protoboard hardware. The first step shows the VHDL code. Before a netlist is developed, the (Verilog or) VHDL is simulated using Mentor Graphics ModelSim for logic and timing verification of the design. This step is not shown in the diagram below. Once the design simulates as intended, then the (Verilog or) VHDL design is transformed/synthesized into a netlist by the Xilinx Project Navigator or Mentor Graphics LeonardoSpectrum Electronic Design Automation (EDA) tools. A netlist is a circuit representation of the Verilog or the VHDL source code. The netlist is then placed, mapped and routed onto a desired FPGA device. The placement, mapping and routing is unique for each type of FPGA and it depends on the internal configuration of the FPGA device. Specifically, the device being used is the Xilinx Spartan II FPGA on the XESS protoboard. Once the design is placed, mapped and routed onto the FPGA, a binary file (bit file) representation is generated for the Spartan II FPGA that can then be downloaded ("burned") into the FPGA to implement the logic. The XESS GSXload utility is used to physically download the bit file into the FPGA. Once the bit file is downloaded, the protoboard is ready to verify the design in hardware.
Created by: David M. Sendek, July 2003